Fan-Out Package Interposer With Controlled Standoff for High I/O Density

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Solution Overview

Problem

Conventional semiconductor packaging technologies face challenges in increasing I/O pad density due to smaller die sizes, leading to issues like solder bridges and warpage, which affect packaging yield and reliability.

Innovation Solution

The development of a package including an interposer with a metal spacer and rigid dielectric layer that defines the standoff distance between the interposer and package, allowing for increased I/O pad density and reducing warpage through controlled spacing and bonding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fan-in packaging is used to maintain die size, then manufacturing cost is reduced, but I/O pad density is limited

Engineering Contradiction:
ImproveI/O pad densityVSAvoidpackaging structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from fan-in packaging (I/O pads confined to die surface area) to fan-out packaging (I/O pads redistributed to a larger area than the die). This dimensional expansion allows I/O pads to be spread across a broader region, increasing pad density without proportionally increasing die size, thereby resolving the contradiction between quantity of I/O pads and device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If I/O pad pitch is decreased to increase density, then I/O pad density is improved, but solder bridges occur

Engineering Contradiction:
ImproveI/O pad densityVSAvoidsolder joint reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces an underfill material as an intermediary substance applied between the die and the substrate. This underfill serves multiple functions: it provides mechanical support to prevent solder ball detachment, fills gaps to avoid solder bridges between closely spaced pads, and compensates for thermal expansion differences. This mediator enables high I/O pad density while maintaining solder joint reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If fan-out packaging is used to increase I/O pad area, then I/O pad density is improved, but warpage occurs

Engineering Contradiction:
ImproveI/O pad densityVSAvoidpackage flatness
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The patent employs underfill material as a counterbalancing element that compensates for the warpage forces generated during fan-out packaging. The underfill provides mechanical support and stress distribution that counteracts the warping tendency, maintaining package flatness while enabling the expanded I/O pad area characteristic of fan-out packaging.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

4Productivity

If die size is reduced to increase integration, then productivity is improved, but packaging difficulty increases

Engineering Contradiction:
Improveintegration densityVSAvoidpackaging ease
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent resolves the packaging difficulty of miniaturized dies by transitioning to fan-out packaging, where the I/O pads are redistributed to a larger area than the die itself. This dimensional expansion separates the die size constraint from the I/O pad arrangement, allowing small dies to achieve high integration density while maintaining packaging ease through the enlarged pad footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11854955B2Fan-out package with controllable standoff
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11854955B2 patent drawing
  • US11854955B2 patent drawing
  • US11854955B2 patent drawing

AI summary

A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.