Fan-Out Voltage Line Layout for Compact Display Panels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices face challenges in reducing the size of non-display areas, protecting electrodes and lines from static electricity, and preventing short-circuit risks in the fan-out area.
Innovation Solution
The display device incorporates a fan-out line in the metal layer of the fan-out area, with first and second voltage lines having plate portions that overlap in the thickness direction, and includes specific layer thicknesses and distances to reduce the fan-out area size and protect against static electricity and short-circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the fan-out area is reduced in size, then the display area can be increased, but the risk of short-circuit and static electricity damage to electrodes and lines increases
Solution Approach 1:
The voltage lines are divided into multiple segments (first voltage line and second voltage line) that are spatially separated and do not overlap in the plan view. This segmentation prevents direct electrical contact between different voltage potentials, reducing short-circuit risk while allowing compact fan-out area design.
Solution Approach 2:
A via layer is introduced as an intermediary structure to vertically connect the first and second voltage lines to different conductive layers. The via layer includes insulating material that prevents direct horizontal contact between voltage lines while enabling vertical electrical connection, thus preventing short-circuits in the reduced fan-out area.
2Area of stationary object
If voltage lines are placed close together to reduce fan-out area, then area is reduced, but static electricity can more easily cause short-circuits between lines
Solution Approach 1:
Different regions of the fan-out area are assigned different functions: the first voltage line region is optimized for high voltage signal transmission, while the second voltage line region is optimized for low voltage signal transmission. This local differentiation allows closer spacing while maintaining electrical isolation through the via layer's insulating structure.
Solution Approach 2:
The patent transitions from two-dimensional planar routing to three-dimensional vertical routing by using the via layer to connect voltage lines at different heights (different conductive layers). This dimensional change allows voltage lines to be closer in plan view without risking short-circuits, as the via layer's insulating material prevents lateral electrical contact.
3Area of stationary object
If overlapping plate portions are used to reduce fan-out area, then area is reduced, but signal interference between voltage lines increases
Solution Approach 1:
The first and second plate portions are positioned at different vertical levels (different conductive layers) connected by the via layer. This vertical separation reduces capacitive coupling and electromagnetic interference between the voltage lines while maintaining compact horizontal footprint, thus reducing signal interference in the reduced fan-out area.
4Length of stationary object
If the distance between conductive layers is reduced to minimize device thickness, then device thickness is reduced, but the risk of breakdown and short-circuit increases
Solution Approach 1:
The via layer is constructed with composite materials including conductive material for vertical electrical connection and insulating material for lateral electrical isolation. This composite structure enables thin device design while maintaining adequate breakdown voltage through the insulating material's dielectric properties.
Solution Approach 2:
The via layer acts as an intermediary structure between conductive layers, providing both electrical connection (through conductive material) and electrical isolation (through insulating material). This dual-function intermediary enables reduced layer spacing while preventing breakdown and short-circuits.
Data Source
AI summary
A display device includes a display area comprising pixels, a fan-out area, a pad area, a display driver, a metal layer disposed on a substrate, a data line, a first voltage line, and a second voltage line extending in a first direction on the metal layer in the display area, a fan-out line electrically connecting the data line to the display driver on the metal layer in the fan-out area, a gate line disposed on the metal layer in the display area and extending in a second direction intersecting the first direction, a source-drain layer disposed on the gate line, and an electrode layer disposed on the source-drain layer. The first voltage line includes a first plate portion disposed on the source-drain layer in the fan-out area, and the second voltage line comprises a second plate portion disposed on the electrode layer in the fan-out area.