Fan-Out Wafer Level Package Alignment Marks

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Solution Overview

Problem

Current methods for producing fan-out wafer level chip-scale packages (FOWLCSPs) face challenges with misalignment during the formation of signal redistribution layers, which can lead to inefficiencies in the manufacturing process.

Innovation Solution

The method involves forming alignment marks in a molding compound using infrared imaging and laser ablation, allowing for precise alignment of semiconductor die and subsequent photolithography operations to prevent misalignment and ensure accurate distribution of electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional alignment methods are used during redistribution layer formation, then the manufacturing process is simpler, but misalignment occurs leading to reduced manufacturing precision

Engineering Contradiction:
Improvealignment precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Alignment marks are formed in the molding compound before photolithography operations begin. These pre-formed marks serve as reference points that guide subsequent alignment processes, ensuring precise positioning of the semiconductor die and redistribution layers without requiring complex real-time alignment mechanisms

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The molding compound serves as an intermediary medium that contains both the semiconductor die and the alignment marks. This intermediary structure provides a stable reference framework that facilitates precise alignment between different layers during manufacturing, resolving the contradiction by embedding alignment references directly into the package structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If alignment marks are formed using infrared imaging and laser ablation, then manufacturing precision is improved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvealignment mark precisionVSAvoidmanufacturing ease
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Traditional mechanical alignment methods are replaced with infrared imaging and laser ablation technologies. The infrared imaging system optically detects alignment features, and the laser ablation system precisely etches alignment marks without mechanical contact, achieving superior precision while maintaining process integration

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The manufacturing process utilizes infrared wavelength imaging rather than visible light, changing the operational parameter to achieve better contrast and precision for alignment mark formation. The laser ablation process also allows precise control of mark depth and dimensions through parameter adjustment, improving precision while keeping the process controllable

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the accuracy and efficiency of the manufacturing process by preventing misalignment, thereby improving the quality and reliability of FOWLCSPs by ensuring precise alignment and distribution of electrical connections.

Implementation Method 1

A location of one or more alignment features within the molding compound can be determined, for example, by infrared imaging

Methodology Applied
Scientific EffectInfrared radiation: Infrared Radiation

Implementation Method 2

one or more alignment marks can be formed in the molding compound based on the determined respective locations

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS11018030B2Fan-out wafer level chip-scale packages and methods of manufacture
Publication Date: 2021.05.25 SEMICON COMPONENTS IND LLC
  • US11018030B2 patent drawing
  • US11018030B2 patent drawing
  • US11018030B2 patent drawing

AI summary

In a general aspect, a for producing a fan-out wafer level package (FOWLP) semiconductor device can include separating a semiconductor wafer into a plurality of semiconductor die and, after separating the semiconductor wafer into the plurality of semiconductor die, increasing spacing between the plurality of semiconductor die. The method can further include encapsulating, in a molding compound, the plurality of semiconductor die and determining respective locations of one or more alignment features disposed within the molding compound. The method can still further include forming, based on the determined respective locations, one or more alignment marks in the molding compound.