Fan-Out Wafer Level Package CTE Mismatch Solution
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Solution Overview
Problem
Conventional wafer level packaging techniques face issues with CTE mismatching between silicon dies and molding compounds, leading to mechanical instability, increased manufacturing costs, and challenges in miniaturization due to thickness and size constraints, as well as complex processes that result in surface warping and high costs.
Innovation Solution
A fan-out wafer level package (FO-WLP) structure with a substrate having pre-formed die receiving cavities and terminal contact metal pads, utilizing an elastic dielectric layer to absorb thermal mechanical stress between the die and substrate, and a redistribution layer to reduce package thickness and improve CTE matching, featuring materials like FR5/BT substrates and silicone dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional molding compound is used to encapsulate silicon die, then the package can be formed, but CTE mismatching occurs causing mechanical instability and location shifting
Solution Approach 1:
The patent introduces an intermediary material layer between the silicon die and the molding compound. This intermediate layer has a CTE value that bridges the gap between silicon (low CTE) and molding compound (high CTE), thereby reducing thermal mechanical stress and preventing location shifting during temperature cycling while maintaining package integrity
Solution Approach 2:
The patent employs composite material structures combining multiple layers with different CTE properties. By creating a composite package structure with carefully selected materials, the overall CTE mismatch is reduced, and mechanical stability is improved while accommodating the thermal expansion differences between silicon die and molding compound
2Reliability
If die are packaged individually using conventional techniques, then each die can be protected, but the manufacturing process becomes time-consuming
Solution Approach 1:
The patent merges multiple individual packaging operations into a single wafer-level processing step. By treating the entire wafer as one object and performing packaging operations on all dies simultaneously before singulation, the manufacturing process is dramatically accelerated while each die still receives adequate protection through the unified package structure
Solution Approach 2:
The patent performs packaging operations in advance on the wafer level before the dies are separated. By completing protection and interconnection operations while the dies are still attached to the wafer, the process eliminates subsequent individual packaging steps, significantly improving manufacturing efficiency without compromising die protection
3Adaptability or versatility
If build up layer is added to redistribute pads, then pad redistribution is achieved, but package thickness increases
Solution Approach 1:
The patent implements pad redistribution in the planar dimension rather than adding vertical thickness. By redistributing pads laterally within the same package plane and utilizing the wafer-level processing capability to reposition connection points, the function of pad redistribution is achieved without increasing package thickness through additional build-up layers
4Manufacturing precision
If complex mold tools and CMP processes are used, then surface warping is controlled, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the need for complex mold tools and CMP processes from the manufacturing workflow. By adopting wafer-level packaging that processes entire wafers simultaneously and uses simpler encapsulation methods, surface flatness is maintained through the inherent stability of the wafer structure without requiring expensive specialized equipment or additional finishing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FO-WLP structure achieves improved CTE performance, reduced package size, and enhanced board-level reliability during temperature cycling, simplifying the manufacturing process and reducing costs by eliminating the need for complex mold tools and CMP processes.
Implementation Method 1
utilizing an elastic dielectric layer to absorb thermal mechanical stress between the die and substrate
Data Source
AI summary
The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.