Fan-Out Wafer Level Packaging Encapsulation Warpage Control
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Solution Overview
Problem
Conventional fan-out wafer level packaging methods result in wafer warpage and topographical discontinuities due to uneven encapsulant thickness, requiring extensive post-processing and potential damage to die units.
Innovation Solution
Simultaneously encapsulating the front and four sides of die units during molding with a balanced encapsulant thickness on both active and back surfaces, using a polymer layer like epoxy film, and applying a fan-in or fan-out redistribution layer to connect bond pads to conductive interconnects, which are plated to a height of at least 20 microns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fan-out wafer level packaging methods are used with uneven encapsulant thickness, then the molding process can be completed, but wafer warpage and topographical discontinuities occur
Solution Approach 1:
The patent applies preliminary action by pre-coating the carrier with an encapsulant layer before placing die units, and by designing mold cavities with predetermined depths. This ensures uniform encapsulant thickness is achieved before the molding process begins, preventing wafer warpage and topographical discontinuities while maintaining ease of manufacture
Solution Approach 2:
The patent changes the parameter of encapsulant thickness from uneven to uniform by controlling the encapsulant layer thickness and mold cavity depth. This parameter control ensures that the encapsulant thickness ratio between active and back surfaces falls within 5:1 to 1:5, resolving the contradiction between manufacturing ease and precision
2Manufacturing precision
If extensive post-processing is performed to correct wafer warpage, then wafer flatness can be improved, but die units may be damaged
Solution Approach 1:
The patent prevents the need for post-processing by applying preliminary actions during molding: pre-coating the carrier with encapsulant and designing mold cavities with controlled depths. This eliminates wafer warpage before it occurs, improving manufacturing precision without requiring post-processing that could damage die units
Solution Approach 2:
The patent converts the potential harm of uneven encapsulant distribution into a benefit by using the encapsulant material itself to create a balanced thickness distribution. The encapsulant is designed to fill mold cavities to predetermined depths, creating uniform thickness that prevents warpage while protecting die units
3Ease of manufacture
If encapsulant thickness is not balanced on active and back surfaces, then the molding process is simpler, but wafer warpage occurs
Solution Approach 1:
The patent applies preliminary action by pre-coating the carrier with an encapsulant layer of controlled thickness before molding. This preliminary step ensures that the encapsulant thickness is balanced on both active and back surfaces, maintaining wafer structural stability while keeping the molding process simple
Solution Approach 2:
The patent changes the encapsulant thickness parameter by controlling the encapsulant layer thickness and mold cavity depth. This ensures the thickness ratio between active and back surfaces falls within 5:1 to 1:5, achieving both manufacturing simplicity and structural stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wafer warpage, eliminates the need for extensive post-processing, and creates a balanced structure with improved connectivity, enhancing the manufacturing efficiency and reliability of semiconductor packages.
Implementation Method 1
The multiple die units and temporary tape carrier are overmolded with a molding compound using a compression molding process
Implementation Method 2
The conductive interconnect may be a plated copper post. The copper posts may be plated over die bond pads on the active surface of the die units
Data Source
AI summary
A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.