Fan-Out Wafer-Level Packaging Alignment Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional fan-out wafer-level packaging processes result in wafer warpage and misalignment of semiconductor chips due to plastic packaging, leading to reduced alignment accuracy and yield in the redistribution layer formation.
Innovation Solution
The method involves forming a fan-out wafer array with semiconductor chips bonded to an adhesive layer, followed by a plastic packaging layer, and then forming a redistribution layer by dividing the wafer array into multiple alignment areas, where each area is exposed separately in the photolithography process to account for offset shifts, improving alignment accuracy through high-precision photolithography alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plastic packaging material is heated and pressed at high temperature during plastic packaging process, then packaging integrity is improved, but wafer warpage increases causing chip misalignment
Solution Approach 1:
The patent divides the wafer into multiple independent packaging regions, each with its own redistribution layer and interconnection structure. This segmentation allows each region to be packaged and tested independently, isolating warpage effects to local areas rather than affecting the entire wafer, thereby maintaining alignment accuracy in each segment despite overall wafer deformation
Solution Approach 2:
The patent performs preliminary packaging of individual chips or small groups of chips before completing the full wafer packaging process. By packaging smaller units first and then integrating them into the complete wafer structure, the process accommodates thermal expansion and warpage that occur during high-temperature plastic packaging, preventing misalignment of the entire wafer
2Productivity
If photolithography alignment is performed on the entire wafer at once, then processing efficiency is improved, but alignment accuracy decreases due to wafer warpage
Solution Approach 1:
The patent segments the photolithography alignment process into multiple stages corresponding to different packaging regions. Each region undergoes alignment and pattern formation separately, allowing the photolithography system to maintain high precision on small local areas rather than attempting to align the entire warped wafer surface at once, thus preserving alignment accuracy while maintaining overall productivity
Solution Approach 2:
The patent introduces a hierarchical dimension to the alignment process by first establishing coarse alignment at the wafer level, then performing fine alignment at the individual packaging region level. This multi-level alignment approach in different dimensional scales allows efficient processing of the entire wafer while maintaining high precision in each local region despite warpage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the alignment accuracy of the redistribution layer, thereby improving the yield of wafer packaging by adjusting the photolithography exposure step for each etching unit, which is feasible with a light shielding structure on the photolithography mask.
Implementation Method 1
performing a photolithography alignment and exposure process separately in one of the multiple patterning areas
Implementation Method 2
followed by an etching process to form through holes in the dielectric layer
Data Source
AI summary
The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.