Fan-Out Wafer Semiconductor Package Stacking
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Solution Overview
Problem
Conventional methods for fabricating semiconductor device packages result in damage to thin semiconductor wafers due to excessive warpage during encapsulation, costly debonding processes, and exposure of semiconductor material during singulation, leading to increased complexity and thermal management issues.
Innovation Solution
The implementation of a fan out wafer-level manufacturing process that reduces the number of components and steps, using a dielectric molding material to laterally separate and secure semiconductor dice, allowing for reduced height and improved thermal management by eliminating the need for a carrier wafer and minimizing stress during singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a carrier wafer is used to support the base wafer during stacking and encapsulation, then mechanical support and handling are improved, but device complexity and manufacturing cost increase due to additional components and debonding processes
Solution Approach 1:
The patent removes the carrier wafer from the manufacturing process entirely. Instead of using a carrier wafer to support the base wafer during stacking and encapsulation, the process directly stacks semiconductor dice on the base wafer and performs encapsulation without any intermediate carrier substrate, thereby eliminating the complexity of carrier attachment and debonding operations
Solution Approach 2:
The patent combines the support function and the final package substrate function into a single entity - the base wafer itself. By eliminating the separate carrier wafer, the base wafer serves both as the mechanical support during processing and as the final package substrate, reducing the total number of components required
2Ease of operation
If a carrier wafer is used to support the base wafer, then handling capability is improved, but manufacturing cost increases due to costly debonding processes
Solution Approach 1:
The patent eliminates the carrier wafer debonding operation by removing the carrier wafer from the process entirely. The base wafer is handled directly throughout the stacking and encapsulation processes using standard wafer handling equipment, eliminating the need for costly laser debonding or chemical debonding operations
Solution Approach 2:
The base wafer is prepared in advance with appropriate handling features and structural characteristics that enable direct handling by standard wafer processing equipment. This preliminary preparation eliminates the need for subsequent carrier attachment and debonding operations, reducing manufacturing complexity and cost
3Productivity
If the base wafer is singulated through the streets between die locations, then individual packages are separated, but semiconductor material is exposed at the sides leading to damage risk
Solution Approach 1:
The patent applies encapsulation material to the base wafer before singulation to cover and protect the semiconductor material at the die streets. This preliminary encapsulation creates a protective barrier that prevents damage during the subsequent singulation process, allowing efficient separation of individual packages without exposing vulnerable semiconductor material
Solution Approach 2:
The encapsulation material serves as a protective cushion applied beforehand to the base wafer. This cushioning layer protects the exposed semiconductor material at the die streets from mechanical damage during singulation, ensuring reliability while maintaining productivity
Data Source
AI summary
Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level. Laterally offset semiconductor dice may be stacked at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice. The laterally offset semiconductor dice may be electrically connected to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer.