Fan-Out Semiconductor Package for Wide I/O on Small Logic Chips
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Solution Overview
Problem
In three-dimensional (3D) chip stacks, especially in mobile applications, logic chips with sizes smaller than the standardized 'wide I/O' interface face challenges in fitting the interface, leading to costly solutions like extending the chip size.
Innovation Solution
The use of a fan-out WLP (wafer level package) or eWLB (embedded wafer level package ball grid array) approach with an extension layer and a redistribution layer (RDL) to increase the chip size and reroute interface connections, allowing the smaller logic chip to accommodate the larger 'wide I/O' interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the chip size is increased to fit the standardized interface, then the interface compatibility is improved, but the chip area available for active circuits is reduced
Solution Approach 1:
The solution divides the chip structure into two distinct parts: the original active chip area and the added extension layer. The extension layer serves as a separate functional region that provides interface compatibility without interfering with the active circuits on the original chip. This segmentation allows the chip to simultaneously maintain its original functionality while gaining interface adaptation capability.
Solution Approach 2:
The invention adds a lateral dimension to the chip structure by extending the chip area in the planar direction rather than increasing thickness. The extension layer is formed laterally from the boundary of the original chip, providing additional area for interface connections without affecting the vertical stacking or the active circuit area on the original chip surface.
2Adaptability or versatility
If the chip size is extended to accommodate the interface, then the interface fitting is improved, but the manufacturing cost increases
Solution Approach 1:
The extension layer is formed using a cost-effective approach that does not require expensive silicon wafer fabrication. Instead, the extension layer can be created using cheaper materials and processes such as molding or bonding techniques, making it a more economical solution compared to extending the actual silicon chip area through additional semiconductor manufacturing steps.
3Adaptability or versatility
If the chip size is increased to fit the interface, then the interface coverage is improved, but the device complexity increases
Solution Approach 1:
The extension layer acts as an intermediary structure between the original chip and the standardized interface. It provides a transition zone that facilitates the connection between the chip's active circuits and the interface requirements, simplifying the overall integration process by decoupling the chip design from the interface constraints.
Data Source
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AI summary
A semiconductor device includes: a semiconductor chip(401); an extension layer (405) extending laterally from a boundary of the semiconductor chip (401a); a redistribution layer (409) disposed over at least one side of the extension layer and the semiconductor chip, wherein the redistribution layer electrically couples at least one contact (410) of the semiconductor chip to at least one contact of an interface (412) , wherein at least a part of the interface extends laterally beyond the boundary of the semiconductor chip.