Display Device Fan-Out Wiring Length Variation
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Solution Overview
Problem
As display devices increase in size, variations in the length and resistance of fan-out wirings lead to signal delay variations, degrading display quality due to differences in resistance among these wirings.
Innovation Solution
The display device design includes varying lengths and widths of data fan-out wirings, with lengths decreasing from the driver IC towards the center and widths increasing, which increases capacitance between data and gate lines, compensating for resistance deviations by adjusting overlapping areas to achieve uniform signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If fan-out wirings are made longer to reach data lines from driver IC, then connection is achieved, but resistance increases causing signal delay variation
Solution Approach 1:
The patent applies local quality by varying the line width of fan-out wirings at different segments. Specifically, the first line width is set larger than the second line width in different regions, creating localized impedance adjustments that compensate for the increased resistance in longer wirings, thereby maintaining uniform signal delay across all data lines.
Solution Approach 2:
The patent changes the physical parameters of the fan-out wirings by adjusting line width and positioning to control capacitance. By modifying these geometric parameters, the patent compensates for resistance variations in fan-out wirings of different lengths, achieving uniform signal delay without requiring equal wiring lengths.
2Reliability
If fan-out wirings are made shorter to reduce resistance, then signal delay improves, but the non-display area becomes larger reducing display area
Solution Approach 1:
The patent allows fan-out wirings to extend to different distances from the driver IC depending on their position, with longer wirings compensated by larger line widths. This localized adaptation enables the non-display area to be minimized while maintaining signal delay uniformity across all data lines.
3Reliability
If all fan-out wirings are made equal length, then signal delay uniformity is achieved, but the non-display area increases and display area decreases
Solution Approach 1:
The patent changes the line width parameter of fan-out wirings to compensate for length variations. By adjusting the line width rather than forcing equal lengths, the patent achieves signal delay uniformity while minimizing the non-display area and maximizing the display area.
4Reliability
If line width is increased to compensate for resistance, then signal delay uniformity improves, but manufacturing complexity increases
Solution Approach 1:
The patent implements local quality by defining specific first and second line widths for different segments of fan-out wirings. This segmented approach with clearly defined width variations achieves signal delay compensation while maintaining a relatively simple manufacturing process compared to more complex compensation methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves uniformity in signal delay by compensating for resistance variations among fan-out wirings, maintaining display quality while allowing for a narrow bezel.
Implementation Method 1
a capacitance between the data lines and the gate lines increases as the length of the corresponding data fan-out wiring decreases
Data Source
AI summary
A display device includes a substrate including a plurality of pixels disposed in a display area of the substrate. A non-display area of the substrate is disposed adjacent to the display area. The display device further includes a plurality of gate lines and a plurality of data lines arranged in a matrix form in the display area on the substrate, at least one driver integrated circuit (IC) disposed in the non-display area on the substrate, and a plurality of data fan-out wirings disposed on the substrate and connecting the data lines and the at least one driver IC. Lengths of the data fan-out wirings vary, and the data lines overlap the gate lines more as the lengths of the corresponding data fan-out wirings decrease.