Cooling Fan Synchronization Using Phase-Locked Speed Control
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Solution Overview
Problem
Conventional cooling systems for electronic circuits face issues due to desynchronization of fans, leading to noise and interference problems.
Innovation Solution
A master-slave coupling system is implemented using a frequency lock status and phase lock loop to synchronize multiple fans, ensuring they rotate at the same speed by adjusting voltages, thereby minimizing noise and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If multiple fans are used to cool electronic circuits, then cooling effectiveness is improved, but noise and interference increase due to desynchronization
Solution Approach 1:
The patent implements a feedback control system where the rotation speed of each fan is monitored and compared against a reference speed. The controller adjusts the voltage supplied to each fan based on the detected speed deviation, ensuring all fans operate at synchronized speeds. This closed-loop feedback mechanism eliminates the beat frequencies and conductive emissions caused by desynchronized fan operation while maintaining effective cooling.
Solution Approach 2:
The patent changes the operational parameters of the fans by dynamically adjusting their rotation speeds to be identical. By controlling the voltage input to each fan motor and monitoring the resulting rotation speed, the system ensures all fans operate at the same speed parameter, thereby eliminating the harmful noise and interference generated by speed differences while preserving the cooling function.
2Productivity
If fan speeds are increased to improve cooling, then heat dissipation is enhanced, but noise and interference problems worsen
Solution Approach 1:
The feedback control system monitors the rotation speed of each fan and adjusts the voltage input to maintain synchronized operation. This allows the system to operate multiple fans at higher speeds for improved heat dissipation while ensuring they remain synchronized, thereby avoiding the noise and interference problems that would otherwise accompany high-speed operation.
3Device complexity
If conventional independent fan control is used, then system complexity is reduced, but synchronization and reliability deteriorate
Solution Approach 1:
The patent introduces a feedback control mechanism where each fan's rotation speed is detected and fed back to a controller. The controller compares the detected speed with a reference speed and adjusts the voltage input accordingly. This feedback system ensures reliable synchronization among all fans while maintaining relatively simple implementation through the use of standard control components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The synchronization of fans reduces noise and interference, maintaining effective cooling while minimizing fan failure impacts, ensuring reliable operation of electronic circuits.
Implementation Method 1
a phase lock loop configured to receive the reference synchronization signals and the slave synchronization signals, provide a comparison between the reference synchronization signals and the slave synchronization signals, and provide the gain pursuant to the comparison
Implementation Method 2
a master voltage controlled oscillator configured to receive input voltages, rotate master blades of the master fan pursuant to the input voltages
Data Source
AI summary
In an illustrative embodiment, a control system to synchronize a number of slave fans to a master fan may include a master voltage controlled oscillator to receive input voltages, rotate master blades of the master fan pursuant to the input voltages, and provide reference synchronization signals; a slave voltage controlled oscillator to receive the input voltages modified by a gain, rotate slave blades of the slave fan at slave fan speed pursuant to the input voltages, and provide slave synchronization signals; and a phase lock loop configured to receive the reference synchronization signals and the slave synchronization signals, provide a comparison between the reference slave synchronization signals, and provide the gain pursuant to the comparison between the reference synchronization signals and the slave synchronization signals.