FanFET DRAM Cell Structure for Sub-4F2 Miniaturization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DRAM devices utilizing vertical transistors have reached a cell size limit of 4F2, making it challenging to further miniaturize memory devices.
Innovation Solution
The development of a DRAM device incorporating vertical current type fan-shaped field effect transistors (FanFETs) with a unique pillar structure and fabrication method, allowing for the formation of transistors with a base, tapered, top, front, and rear side faces, and alternating isolation stripes to achieve a cell size of less than 4F2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical transistors are stacked below or above cell capacitors to reduce cell size, then cell size is reduced to 4F2, but further miniaturization below 4F2 cannot be achieved
Solution Approach 1:
The patent transitions from planar transistor layouts to a three-dimensional FanFET structure where the channel extends vertically from the substrate surface. This dimensional change allows the transistor to occupy less footprint area while maintaining functional channel length, enabling cell sizes below the 4F2 limit achieved by conventional vertical stacking approaches.
Solution Approach 2:
The FanFET channel is segmented into multiple regions including a body region, source region, and drain region, with the channel extending vertically and tapering toward the surface. This segmentation allows optimized electrical characteristics in different regions while maintaining a compact footprint, resolving the contradiction between size reduction and functional performance.
2Ease of manufacture
If conventional vertical transistors are used with alternating isolation stripes, then manufacturing is simplified, but cell size cannot be reduced below 4F2
Solution Approach 1:
The FanFET structure employs asymmetric geometry where the channel tapers from a wider base at the substrate surface to a narrower top at the surface level. This asymmetric shape is achieved through selective etching processes that remove material preferentially from certain regions, allowing compact cell size while maintaining manufacturability through established semiconductor fabrication techniques.
Solution Approach 2:
Different regions of the FanFET structure have locally optimized properties: the body region maintains a wider cross-section for structural support and gate control, while the channel region tapers to reduce footprint. The source and drain regions have distinct doping profiles optimized for their respective functions. This local quality optimization enables size reduction without compromising manufacturing feasibility.
Data Source
AI summary
The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows. The transistors on one side of each first isolation stripe and the transistors on the other side of said one first isolation stripe are staggeredly arranged. Each word line corresponds to one of the columns and connects the gate conductors of the transistors along the corresponding column. Each capacitor corresponds to one of the transistors and connects the source region of the corresponding transistor.