FanFET Transistor Structure for High Density Memory Integration
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Solution Overview
Problem
Current semiconductor memory devices, particularly 3D-NAND flash memory, face challenges in increasing bit density and reducing bit cost while maintaining high integration and fast access speeds, which are essential for advanced nonvolatile memory applications.
Innovation Solution
The development of a transistor structure known as the FanFET (Fan-structured Field Effect Transistor) with a tapered substrate and a gate embedded in a gate dielectric layer, along with specific geometries and isolation layers, enhances the performance of logic gates and memory cells by improving integration and access speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional transistor structures are used, then device fabrication is simpler, but bit density and integration are limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FanFET structures with gates embedded in dielectric layers at angles (e.g., 45 degrees) relative to the substrate. This dimensional change allows multiple gates to control a single channel from different spatial directions, increasing the effective gate control area and enabling higher bit density without proportionally increasing fabrication complexity
Solution Approach 2:
The FanFET structure embeds multiple gate electrodes within a gate dielectric layer that is itself embedded in the substrate. The gates are nested at different orientations (e.g., first gate at +45°, second gate at -45°) within the same vertical space, allowing compact integration of multiple control elements that enhance channel control while maintaining space efficiency for higher density
2Quantity of substance
If transistor geometry is optimized for higher density, then bit density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric gate orientations within the FanFET structure, with gates positioned at specific angles (e.g., +45° and -45°) relative to the substrate normal. This asymmetric arrangement optimizes the control electric field distribution across the channel while maintaining manufacturability, as the angles can be controlled within standard fabrication tolerances without requiring ultra-precise symmetric alignment
Solution Approach 2:
The gate dielectric layer is selectively embedded in the substrate only in regions where FanFET structures are formed, while other regions maintain conventional planar structures. This local implementation allows high-density FanFET regions to coexist with standard circuit areas, concentrating the geometric precision requirements to specific high-value regions rather than the entire device
3Quantity of substance
If integration is increased, then bit density improves, but access speed may deteriorate
Solution Approach 1:
By introducing vertical dimensionality with gates embedded at angles in the substrate, the FanFET achieves stronger gate control over the channel without increasing lateral device footprint. The multi-directional gate control from different vertical angles enhances carrier modulation efficiency, maintaining fast switching speeds even as devices are scaled and integrated at higher densities
Solution Approach 2:
The channel control is segmented into multiple independent gate electrodes positioned at different orientations within the gate dielectric layer. Each gate segment can independently control carrier flow in its specific directional component, allowing sophisticated control of current modulation that maintains high switching speeds while enabling compact integration of multiple functional elements
Data Source
AI summary
A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The gate is embedded in the gate dielectric layer. The transistor structure density can be improved.