Fan-Out Packaging Layout With Vertical Chip Stacking
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Solution Overview
Problem
Existing fan-out packaging technologies face challenges with large area and thickness, cumbersome processes, and low reliability due to limited distribution accuracy, making it difficult to achieve high-density, low-power consumption, and fast data processing in semiconductor chip packaging.
Innovation Solution
A fan-out chip packaging method involving a support substrate, separation layer, passivation layer, semiconductor chip, redistribution layer, metal bumps, adapter board, and filling layer, which enables three-dimensional vertically stacked packaging, improving integration level and reducing power consumption by shortening conduction paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fan-out wafer level packaging (FOWLP) is used to achieve more I/O and better integration flexibility, then integration flexibility is improved, but package area and thickness become relatively large
Solution Approach 1:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical stacking by placing multiple semiconductor chips at different heights on the same substrate area. Chips are stacked vertically with redistribution layers connecting different levels, enabling high integration without increasing package footprint area.
2Adaptability or versatility
If fan-out wafer level packaging (FOWLP) is used to achieve more I/O and better integration flexibility, then integration flexibility is improved, but package thickness increases
Solution Approach 1:
Multiple semiconductor chips are nested vertically within a compact three-dimensional structure on the substrate. Each chip is positioned at a different height level, with redistribution layers and conductive vias nesting within the vertical space to connect layers, achieving high integration without excessive thickness increase.
3Ease of manufacture
If existing fan-out packaging technology is used, then packaging can be achieved, but manufacturing process becomes cumbersome and reliability is low due to limited distribution accuracy
Solution Approach 1:
The manufacturing process is segmented into standardized modular steps: substrate preparation, chip mounting at specific positions, redistribution layer formation, and vertical stacking. Each module uses standardized procedures with precise positioning fixtures, making the process both simple to execute and highly accurate in distributing chips and connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively integrates multiple chips into a single packaging structure, enhancing integration level, reducing power consumption, and increasing data processing capacity and transmission speed.
Implementation Method 1
performing laser etching on the passivation layer and the first packaging layer to form a groove
Data Source
AI summary
The present disclosure provides a fan-out packaging structure and a method of fabricating the same. The fan-out packaging structure includes a redistribution layer, a passivation layer, a semiconductor chip, a first packaging layer, a groove, first metal bumps, second metal bumps, an adapter board, a stacked chip package, a passive element, and a filling layer. By means of the present disclosure, various chips performing different functions can be integrated into one packaging structure, thereby improving the integration level of the fan-out packaging structure. By means of the redistribution layer, the adapter board, and the first and second metal bumps, a three-dimensional vertically stacked packaging is achieved. As the result, in addition to improved integration level, the conduction paths in the packaging structure can be effectively shortened, thereby reducing power consumption, increasing the transmission speed, and increasing the data processing capacity.