Fan-out Antenna Packaging Structure and Method
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Solution Overview
Problem
Conventional antenna structures on circuit boards result in large volumes, poor conformity, and high production costs due to direct fabrication, which contradicts the requirements for miniaturization and portability in high-tech electronics.
Innovation Solution
A fan-out antenna packaging method involving a supporting substrate, separating layer, semiconductor chip, packaging layer, rewiring layer, and stacked antenna structures, where the packaging layer is pulled out to expose the chip surface, forming through holes for metal bumps, and using materials like epoxy molding layers to reduce warpage and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an antenna is directly fabricated on the surface of a circuit board, then the antenna can be integrated with the circuit board, but the antenna occupies additional area resulting in large volume and poor conformity
Solution Approach 1:
The patent merges the antenna structure with the semiconductor chip packaging structure by forming the antenna on the packaging layer that surrounds the chip. The antenna metal layers are integrated into the packaging process, combining what were previously separate components (antenna and chip package) into a single integrated structure, thereby reducing overall volume while maintaining integration benefits
Solution Approach 2:
The patent transitions from planar antenna fabrication on the circuit board surface to three-dimensional antenna structures formed within the packaging layer above the chip. By utilizing the vertical dimension and stacking multiple antenna metal layers at different heights, the design achieves better spatial utilization and conformity while reducing the horizontal area occupied
2Adaptability or versatility
If an antenna is directly fabricated on the surface of a circuit board, then the antenna can be integrated with the circuit board, but the production costs increase
Solution Approach 1:
The patent combines the antenna fabrication process with the existing semiconductor packaging process. The antenna metal layers are formed using the same packaging layer materials and processing steps already established for chip packaging, eliminating the need for separate antenna manufacturing and assembly operations, thereby reducing production costs while maintaining integration
Solution Approach 2:
The packaging layer serves multiple functions simultaneously: it provides mechanical support for the chip, electrical insulation, and the substrate for the antenna structure. This multi-functionality eliminates the need for dedicated antenna-specific materials and processes, reducing overall manufacturing complexity and cost
3Ease of operation
If the packaging layer is pulled out from the separating layer, then the front surface of the semiconductor chip is exposed, but additional process steps are required
Solution Approach 1:
The separating layer is pre-formed on the supporting substrate before the packaging layer is applied. This preliminary preparation enables easy separation and chip exposure in subsequent steps without requiring complex processing, as the separating layer is designed to be readily removable after serving its protective function
4Reliability
If through holes are formed in the packaging layer for metal bumps, then electrical connectivity is achieved, but the packaging layer structure is modified
Solution Approach 1:
The electrical connectivity is achieved by segmenting the packaging layer to create through holes, which are then filled with metal bumps. This segmentation allows selective penetration of the packaging layer at specific locations to establish electrical connections while preserving the overall integrity and protective function of the packaging structure
Data Source
AI summary
Disclosed is a fan-out antenna packaging method. A front surface of a semiconductor chip is jointed to a top surface of a separating layer; side surfaces and a bottom surface of the semiconductor chip are merged into a packaging layer; the packaging layer is separated from the separating layer to expose the front surface of the semiconductor chip; a rewiring layer is electrically connected to the semiconductor chip; a first antenna structure and a second antenna are stacked on a top surface of the rewiring layer, the antenna structures is electrically connected to the rewiring layer; a through hole runs through the packaging layer and exposes a metal wiring layer in the rewiring layer; and a metal bump electrically connected to the metal wiring layer is formed by using the through hole.


