Fan-Out Antenna Packaging Structure for RF Chip Integration
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Solution Overview
Problem
Existing fan-out wafer level packaging methods for radio frequency chips require large antennas on PCBs to ensure antenna gain, leading to increased PCB area and packaging size, which is inefficient in terms of space and integration.
Innovation Solution
A fan-out antenna packaging structure that includes a semiconductor chip, a plastic packaging material layer, a conductive pole, an antenna structure with alternately stacked dielectric and metal antennas, and a redistribution layer, allowing for compact packaging and improved antenna gain without expanding the PCB area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antennas are laid out directly on PCB to ensure antenna gain, then antenna gain is improved, but PCB area increases
Solution Approach 1:
The patent merges the antenna structure with the packaging structure by integrating the antenna into the plastic packaging material layer. The antenna is formed using the same molding process that creates the packaging encapsulation, combining two previously separate functions (antenna and packaging) into a single integrated structure. This eliminates the need for separate PCB antenna layouts while maintaining antenna performance.
Solution Approach 2:
The patent transitions the antenna from a planar 2D layout on PCB to a three-dimensional structure embedded within the packaging material. The antenna can utilize the vertical dimension and internal volume of the packaging structure, allowing for more compact designs that maintain or improve antenna gain without increasing the footprint area.
2Reliability
If antenna size is increased to ensure antenna gain, then antenna gain is improved, but packaging size increases
Solution Approach 1:
The antenna structure is merged with the packaging encapsulation, allowing the antenna to utilize the packaging material itself as the substrate and enclosure. This integration enables the antenna to achieve adequate gain within the existing packaging volume without requiring additional space, as the packaging structure serves dual purposes.
Solution Approach 2:
The antenna is nested within the packaging structure, with the antenna elements embedded in the plastic packaging material layer. This nesting approach allows the antenna to occupy the internal volume of the packaging rather than requiring external space, maintaining compact overall dimensions while providing sufficient antenna performance.
3Reliability
If external antennas are connected via PCB interfaces, then antenna functionality is achieved, but integration density decreases
Solution Approach 1:
The patent merges the antenna function directly into the packaging structure, eliminating the need for separate external antenna connections and PCB interface circuits. The antenna elements are formed as integral parts of the packaging structure through molding, reducing the number of discrete components and interconnections required, thereby improving integration density.
Solution Approach 2:
The packaging structure is designed to perform multiple functions simultaneously: it provides mechanical encapsulation and protection for the chip, serves as the antenna substrate and enclosure, and integrates the antenna elements directly. This multi-functionality eliminates the need for separate antenna components and interfaces, improving overall integration density.
Data Source
AI summary
The present disclosure provides a fan-out antenna packaging structure and a preparation method thereof. The fan-out antenna packaging structure comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip, a via being formed in the plastic packaging material layer; a conductive pole located in the via and running through the plastic packaging material layer from top to bottom; an antenna structure located on a first surface of the plastic packaging material layer and electrically connected with the conductive pole; a redistribution layer located on a second surface of the plastic packaging material layer and electrically connected with the semiconductor chip and the conductive pole; and a solder bump located on a surface of the redistribution layer, electrically connected with the redistribution layer and insulated from the plastic packaging material layer.