Fan-out Buffer Skew Control via TDR Waveform Analysis
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Solution Overview
Problem
Fan-out buffers in logic circuits face challenges in simultaneously controlling internal and external circuit skews, leading to signal overload and improper signal transfer, which affects the testing and verification of semiconductor wafers during the testing process.
Innovation Solution
A fan-out buffer system that includes delay circuits, edge-to-pulse converters, and a stop pulse signal generator to detect and calibrate signal skews by generating delay control signals based on time domain reflectometry waveforms, ensuring proper signal alignment and transfer between internal and external circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a buffer is connected between the logic circuit and other logic circuits to handle great fan-out, then the signal transfer capability is improved, but the skew control between internal and external circuits becomes difficult
Solution Approach 1:
The patent introduces delay control circuits as intermediary components between the buffer and external circuits. These delay control circuits act as mediators that independently adjust the timing of signals in each channel, enabling precise skew control without affecting the overall signal transfer capability provided by the buffer.
Solution Approach 2:
The patent implements dynamic skew control by making delay times adjustable through delay control circuits. The delay amounts are not fixed but can be dynamically modified based on actual skew conditions, allowing the system to adapt and optimize timing alignment in real-time for different operating conditions.
2Measurement precision
If delay control circuits are added to each channel to control skew, then the skew calibration precision is improved, but the device complexity increases
Solution Approach 1:
The patent applies partial action by implementing delay control circuits only in channels where skew calibration is needed, rather than uniformly across all channels. The delay control amount is also adjusted to be just sufficient for calibration purposes, avoiding unnecessary complexity from excessive delay control capability.
Solution Approach 2:
The patent controls skew by changing the delay time parameter in each channel through delay control circuits. By adjusting this single critical parameter, the system achieves precise skew calibration without needing to modify other circuit parameters or structures, thereby limiting the increase in complexity.
3Manufacturing precision
If the delay time is adjusted to calibrate skew, then the signal alignment is improved, but the internal circuit delay and external circuit delay cannot be simultaneously controlled
Solution Approach 1:
The patent segments the delay control function into separate delay control circuits for internal circuits and external circuits. Each segment operates independently to control its respective delay, allowing simultaneous adjustment of both internal and external circuit delays without interference, thereby achieving comprehensive signal alignment.
Solution Approach 2:
The delay control circuits are designed with universal functionality to handle both internal circuit delay and external circuit delay calibration. Each delay control circuit can independently adjust delay times to compensate for variations in both internal buffer characteristics and external transmission line conditions, providing versatile skew control.
Data Source
AI summary
Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.