Fan-Out Chip Package Structure for TSV-Free 3D Chip Stacking
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Solution Overview
Problem
Current Wafer Level Packaging (WLP) technology does not allow for chip-stacking, leading to complicated and costly conventional chip-stacking techniques that require technologies like Through Silicon Via (TSV), Through Glass Via (TGV), or Wire-bond for vertical connections.
Innovation Solution
A method involving placing a chip layer over a carrier with chip connectors, molding, thinning, adding a metal layer, removing the carrier, and forming a redistribution layer to create a package that enables chip stacking without TSV or similar technologies, using semiconductor, inorganic, and metallic materials for connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional chip-stacking technology is used with TSV, TGV, or Wire-bond for vertical connections, then chip stacking is achieved, but the packaging process becomes complicated and costly
Solution Approach 1:
The patent extracts and eliminates the need for complex vertical connection technologies (TSV, TGV, Wire-bond) by reconfiguring the chip stacking approach. Instead of creating vertical vias through substrates, the invention uses a planar organic substrate with conductive traces that route signals horizontally, thereby removing the disturbing complex vertical connection processes while maintaining chip stacking functionality
Solution Approach 2:
The patent inverts the conventional approach by instead of connecting chips vertically through complex via structures, it uses a planar organic substrate where conductive traces route signals in a flattened configuration. This inversion transforms the three-dimensional vertical connection problem into a two-dimensional planar routing solution, simplifying the overall packaging process
2Reliability
If conventional chip-stacking technology with TSV, TGV, or Wire-bond is used, then vertical connection between stacked chips is achieved, but manufacturing cost increases
Solution Approach 1:
The patent employs an organic substrate that can be manufactured using low-cost printing or coating techniques rather than expensive semiconductor fabrication processes. This disposable-like approach to the interconnection substrate dramatically reduces manufacturing costs while maintaining sufficient reliability for the application, replacing costly TSV/TGV structures with affordable organic circuit boards
Solution Approach 2:
The patent substitutes the mechanical drilling and plating processes required for TSV/TGV with a chemical printing or coating process for creating conductive traces on the organic substrate. This replacement of mechanical fabrication with chemical deposition significantly reduces manufacturing complexity and cost while achieving the same electrical interconnection function
3Productivity
If Wafer Level Packaging (WLP) technology is used, then manufacturing process is streamlined, but chip-stacking is not allowed
Solution Approach 1:
The patent segments the packaging function by separating the wafer-level packaging process from the chip stacking function. The organic substrate is divided into regions with different functions (signal routing, power distribution, mechanical support), allowing WLP to be applied to individual chip layers while the segmented substrate enables stacking of multiple such layers through simplified interconnection
Data Source
AI summary
A method of forming a package comprises assembling at least one chip layer over a carrier substrate, the at least one chip layer including chip couplers and chips, each of the chips having a front side facing the carrier substrate and chip contacts formed on the front side, the couplers including first chip couplers, each of the first chip couplers having an upper side facing away from the carrier substrate and first bumps formed on the upper side. The method further comprises encapsulating the at least one chip layer to form a molded package structure, thinning the molded package structure to expose the first bumps, forming a metal layer on a side of the molded package structure where the first bumps are exposed, removing the carrier to expose another side of the molded package structure, and forming a redistribution layer and second bumps on the molded package structure.