Fan-Out Semiconductor Package With Integrated Coil And Dummy Patterns
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Solution Overview
Problem
Current fan-in semiconductor packages face challenges in accommodating a large number of I/O terminals and compact size requirements, leading to spatial limitations and difficulties in direct mounting on electronic device main boards, while fan-out packages aim to address these issues by redistributing connection terminals outwardly, but struggle with power supplying efficiency and cost-effectiveness.
Innovation Solution
The fan-out semiconductor package incorporates a coil pattern layer and a dummy pattern layer in its redistribution structure, with the coil pattern layer acting as a power inductor and the dummy pattern layer adjusting the metal ratio to enhance power efficiency and reliability, reducing the need for separate power inductors and minimizing warpage due to thermal expansion mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fan-in semiconductor package structure is used, then compact size is achieved, but spatial limitations occur and direct mounting on main boards becomes difficult
Solution Approach 1:
The patent transitions from fan-in configuration where connection terminals are confined within the chip footprint to fan-out configuration where terminals are redistributed outwardly beyond the chip boundaries. This dimensional redistribution enables direct mounting on main boards while preserving compact package volume through vertical stacking and lateral extension of connection members.
Solution Approach 2:
The connection structure is divided into multiple segments: a first connection member extending from the inactive surface through the chip thickness, and a second connection member extending from the active surface. This segmentation allows independent optimization of each connection path, enabling both compact packaging and enhanced mounting versatility.
2Adaptability or versatility
If fan-out package redistributes connection terminals outwardly, then mounting capability is improved, but power supplying efficiency deteriorates
Solution Approach 1:
The patent merges the power delivery function with the connection member structure by forming coil patterns directly on the first and/or second connection members. This integration eliminates separate power inductor components and reduces the number of discrete elements, thereby improving power supplying efficiency while maintaining the fan-out mounting capability.
Solution Approach 2:
The connection members serve as intermediaries that simultaneously perform mechanical connection, electrical signal transmission, and power delivery functions. By incorporating coil patterns into these intermediary structures, the patent achieves efficient power transfer without requiring additional dedicated power components.
3Use of energy by moving object
If coil pattern layer is added to redistribution structure, then power supplying efficiency is improved, but device complexity increases
Solution Approach 1:
The connection members are designed to perform multiple functions simultaneously: mechanical support, electrical connection, signal transmission, and power delivery through integrated coil patterns. This multi-functionality reduces the need for separate dedicated components, thereby improving power efficiency without proportionally increasing device complexity.
Solution Approach 2:
The coil patterns are formed as integral parts of the connection member structure during the same manufacturing process, merging what would traditionally be separate components. This integration approach improves power supplying efficiency while minimizing the increase in structural complexity.
4Reliability
If dummy pattern layer is added to adjust metal ratio, then reliability is improved, but device complexity increases
Solution Approach 1:
The dummy pattern layer modifies the metal ratio and thermal mass distribution within the connection member structure to compensate for thermal expansion mismatches between different materials. By adjusting these parameters, the patent improves reliability under thermal cycling while adding only a single pattern layer that can be integrated into existing manufacturing processes.
Solution Approach 2:
The dummy pattern layer acts as a pre-designed compensatory structure that anticipates and counteracts thermal expansion stresses before they cause damage. This proactive approach enhances reliability by balancing thermal forces in advance, rather than requiring complex reactive measures after thermal issues arise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves power supplying efficiency, reduces manufacturing costs, and enhances the reliability and compactness of the semiconductor package, allowing for direct mounting on electronic device main boards without the need for separate interposer substrates.
Implementation Method 1
the coil pattern layer acting as a power inductor
Implementation Method 2
minimizing warpage due to thermal expansion mismatches
Data Source
AI summary
A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and at least one of the first connection member and the second connection member includes a dummy pattern layer.