Fan-Out Packaging Ground Layer for Dense RDL and Plating Stability
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Solution Overview
Problem
Conventional fan-out wafer or panel level packaging technologies face challenges with high wiring density, which leads to complex RDL disposition, degraded electrical performance, and increased manufacturing costs. Additionally, the quality of the plating layer during copper plating processes is critical for improving yield and contact resistance but is often compromised by attempts to slow the plating rate or improve process conditions, resulting in reduced process speed and reproducibility.
Innovation Solution
The method involves forming an additional ground (GND) layer on a fan-out packaging substrate, which reduces wiring density, improves electrical and mechanical reliability, and enhances plating quality. This additional GND layer is formed in directions toward four sides or at least two opposite sides of a die and is electrically connected to GND seal rings or pads to provide a rebuilt GND seal ring or pad. The GND layer also supports the electroplating process by providing additional conductive paths, thereby increasing the plating rate and improving the quality of the redistribution layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of connections between chips increases to achieve higher integration, then the functionality and performance of the packaging device is improved, but the wiring density of the RDL layer increases which degrades electrical performance and increases manufacturing complexity
Solution Approach 1:
The patent introduces an additional GND layer positioned between the substrate and the first RDL layer, adding a new dimensional element to the packaging structure. This additional layer provides extra conductive paths and grounding options without increasing the planar wiring density of existing RDL layers, thereby enabling more connections while maintaining electrical performance.
2Manufacturing precision
If the plating rate is slowed down or process conditions are improved to enhance plating layer quality, then the yield and contact resistance are improved, but the process speed is reduced and reproducibility cannot be achieved
Solution Approach 1:
The patent modifies the electrical parameters of the system by adding an additional GND layer, which changes the current distribution and electrical field characteristics during the electroplating process. This parameter change enables improved plating quality through better current uniformity and reduced resistance, while maintaining fast plating rates and process reproducibility.
3Quantity of substance
If the wiring density of the RDL layer is increased to accommodate more connections, then the number of I/O pins is increased, but the electrical performance is degraded and manufacturing costs increase
Solution Approach 1:
The patent segments the grounding function by introducing a separate additional GND layer distinct from the signal-carrying RDL layers. This segmentation allows the RDL layers to focus on signal transmission with optimized wiring patterns, while the dedicated GND layer provides multiple grounding paths, thereby increasing the effective number of I/O connections without degrading electrical performance.
4Ease of manufacture
If conventional packaging processes are used without an additional GND layer, then the manufacturing process is simpler, but the electrical and mechanical reliability is reduced and plating quality is compromised
Solution Approach 1:
The patent implements the additional GND layer early in the manufacturing sequence, before the first RDL layer is formed. This preliminary action establishes a robust grounding foundation that simplifies subsequent manufacturing steps by providing a stable reference plane for electroplating and wiring operations, thereby improving reliability without significantly complicating the overall process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the additional GND layer reduces wiring density, improves electrical performance, and enhances manufacturing efficiency. It also ensures reproducibility and stability of the electroplating process, leading to higher quality redistribution layers and reduced defects. This results in a high-performance, high-reliability fan-out packaging device with improved thermal management and mechanical stability.
Implementation Method 1
forming a redistribution layer (RDL) on the first dielectric layer and the first via hole... supports the electroplating process by providing additional conductive paths
Data Source
AI summary
Disclosed is a method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method including forming an additional GND layer on a part of a fan-out packaging substrate, forming a first dielectric layer having a first via hole on the additional GND layer, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole, forming a second dielectric layer having a second via hole on the redistribution layer, and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein the additional GND layer is formed in directions toward four sides or at least two opposite sides of a die.