Fanout Interposer Chiplet Routing for High-Density Multi-Die Packaging
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in integrating multiple components within smaller spaces while maintaining high input/output density and efficient interconnectivity.
Innovation Solution
The integration of an interposer chiplet within a semiconductor package, which provides fine routing between components and is embedded within an encapsulation layer along with conductive pillars for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple components are integrated within a single package to increase I/O density, then the number of dies and features increase, but the space available for each component decreases and routing complexity increases
Solution Approach 1:
The patent transitions from planar 2D routing to three-dimensional routing by stacking components vertically and using through-silicon vias (TSVs) to connect different layers. This dimensional change allows multiple dies to be integrated in a compact space without proportionally increasing the package footprint, effectively resolving the contradiction between increasing die count and maintaining available space.
Solution Approach 2:
The patent introduces an interposer as an intermediary substrate that facilitates connections between multiple dies. The interposer provides a centralized routing layer with TSVs that act as mediators, enabling efficient electrical connections between stacked components without requiring direct complex routing between each die pair, thus managing routing complexity while integrating multiple dies.
2Reliability
If fine pitch routing is implemented within redistribution layers to connect adjacent dies, then interconnectivity efficiency improves, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent moves routing from the horizontal plane to the vertical dimension by implementing through-silicon vias (TSVs) that traverse the interposer thickness. This vertical routing approach achieves fine pitch interconnectivity without the manufacturing difficulties of ultra-fine horizontal trace routing, as TSVs can be formed using standard semiconductor fabrication processes.
Solution Approach 2:
The interposer acts as an intermediary that consolidates routing functions into a dedicated substrate with pre-formed TSVs and redistribution layers. This separates the routing complexity from the die design, allowing standard dies to be connected through the interposer's standardized interface, thereby improving ease of manufacture while maintaining interconnectivity efficiency.
3Quantity of substance
If component density is increased within a single package, then I/O density improves, but packaging process complexity and yield challenges increase
Solution Approach 1:
The patent segments the packaging system into modular components: multiple dies, an interposer, and an encapsulant. This segmentation allows each component to be manufactured and tested independently using standard processes, then assembled into a multi-die package. The modular approach maintains high component density while improving yield by isolating defects to individual modules rather than requiring perfect integration of all components simultaneously.
Solution Approach 2:
The interposer serves as a mediator that simplifies the packaging process by providing a pre-configured routing substrate. Dies are attached to the interposer in a controlled sequence using standard wire bonding or flip-chip processes, rather than requiring complex simultaneous alignment of multiple dies. This intermediary approach enables high component density while maintaining packaging yield through process simplicity.
Data Source
AI summary
Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.