Integrated Fan-Out Package Layout Method for Coupling Effect Prediction
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Solution Overview
Problem
Ensuring the reliability and performance of integrated fan-out packages, which face challenges due to scaling down and increased coupling effects between the fan-out substrate and the die, necessitating effective design-stage prediction and adjustment of interconnect and redistribution layers.
Innovation Solution
A layout method that involves establishing and merging data for interconnect and redistribution layers, extracting capacitance and inductance information, and iteratively re-routing or adjusting conductive bumps and dielectric layers to meet performance standards, thereby predetermining and optimizing the coupling effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the package size is reduced to achieve compactness, then the area utilization is improved, but the coupling effect between fan-out substrate and die increases
Solution Approach 1:
The patent applies preliminary action by extracting capacitance and inductance information from merged layout data before manufacturing, allowing the coupling effect to be predicted and optimized in advance. The layout method determines package performance early in the design stage by analyzing capacitance between interconnect layers and inductance of signal paths, enabling adjustments to be made before fabrication to minimize harmful coupling effects while maintaining compact dimensions
2Quantity of substance
If continuous improvement in integration density is achieved through feature size reduction, then the number of components per area is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent replaces manual or trial-and-error layout optimization with an automated computer-based system that extracts capacitance and inductance information from merged layout data. This computational approach substitutes complex manual analysis and iterative adjustments with automated algorithms that calculate electrical parameters and determine package performance, significantly reducing manufacturing complexity while enabling continuous integration density improvement
3Reliability
If the focus is placed on ensuring reliability through design-stage optimization, then the performance prediction is improved, but the design time and computational resources increase
Solution Approach 1:
The patent extracts specific electrical parameters (capacitance between interconnect layers and inductance of signal paths) from the complete merged layout data, focusing computational resources on the most critical factors affecting package performance. By extracting only the relevant capacitance and inductance information needed for performance determination rather than analyzing all layout parameters, the method achieves accurate reliability prediction while minimizing design time and computational resource requirements
Data Source
AI summary
An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.