Fan-Out Package Metal Pattern Layer Electrical Connection

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Solution Overview

Problem

Current fan-out semiconductor packages face challenges in reducing production time, controlling plating quality, eliminating pretreatment limitations, and thinning the package thickness while maintaining electrical connectivity and signal integrity.

Innovation Solution

The introduction of a first metal pattern layer on the backside of the package using a detachable carrier and a second metal pattern layer formed through a plating process, which electrically connects to the frame via a path, eliminating the need for a via plating process and allowing for a reverse order of seed and plated layers, simplifying pretreatment and reducing thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a via plating process is used to connect metal pattern layers, then electrical connectivity is achieved, but production time increases and plating quality control becomes difficult

Engineering Contradiction:

Improveelectrical connectivityVSAvoidproduction time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and eliminates the via plating process from the manufacturing flow. Instead of forming vias and plating them to achieve electrical connection, the invention uses a direct metal pattern layer configuration where the first metal pattern layer on the backside directly connects to the second metal pattern layer through a simplified interface, removing the intermediate via formation step entirely.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the conventional approach by placing the first metal pattern layer on the backside of the package rather than forming connections from the front side through vias. This inversion allows for direct electrical connection without requiring through-hole via plating, thereby reducing production time and simplifying the process flow.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If a via plating process is used to connect metal pattern layers, then electrical connectivity is achieved, but plating quality control becomes difficult

Engineering Contradiction:

Improveelectrical connectivityVSAvoidplating quality

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent removes the via plating process from the manufacturing sequence, eliminating the source of plating quality issues. By using a direct metal pattern layer connection approach on the backside, the invention avoids the complex plating operations required for via formation, thereby improving manufacturing precision and quality control.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If conventional metal pattern layer connection methods are used, then electrical connectivity is achieved, but package thickness increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidpackage thickness

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent inverts the conventional connection approach by establishing electrical connectivity on the backside of the package rather than extending connections through the package thickness from the front side. This inversion enables direct connection between metal pattern layers without requiring thick via structures, thereby reducing overall package thickness.

Inventive Principle:

Principle #13The other way round (Inversion)

4Manufacturing precision

If pretreatment processes are applied to metal layers, then plating quality improves, but production time increases and process limitations arise

Engineering Contradiction:

Improveplating qualityVSAvoidproduction time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent extracts and eliminates the pretreatment process step from the manufacturing flow. By using a direct metal pattern layer configuration that does not require via plating, the invention removes the need for surface preparation, cleaning, and activation treatments that would otherwise be required before plating, thereby reducing production time and eliminating process limitations.

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach shortens production time, improves plating quality, reduces package thickness, and maintains excellent signal and power characteristics by eliminating the via process, thereby enhancing the overall reliability and efficiency of the semiconductor package.

Implementation Method 1

a second metal pattern layer formed through a plating process

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11152292B2Fan-out semiconductor package having metal pattern layer electrically connected embedded semiconductor chip and redistribution layer

Publication Date: 2021.10.19 SAMSUNG ELECTRONICS CO LTD

AI summary

The present invention provides a fan-out semiconductor package, and the fan-out semiconductor package includes a semiconductor chip, an encapsulant covering the semiconductor chip, a connection structure disposed below the semiconductor chip and including a redistribution layer, and first and second metal pattern layers disposed on different levels on the semiconductor chip. The first metal pattern layer is to electrically connect to an electrical connection member such as a frame, provided for electrical connection of the fan-out semiconductor package in a vertical direction through a path via the second metal pattern layer.