Fanout Module With Voids For Optical Interface Access
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Solution Overview
Problem
Current photonic integrated circuit architectures face challenges in achieving high-density, short-distance interconnection with semiconductor chips while maintaining accessibility for optical fiber coupling, which limits performance and efficiency.
Innovation Solution
The proposed solution involves a semiconductor package architecture with a first mold layer encasing a photonic integrated circuit and a redistribution layer providing electrical pathways to a semiconductor chip, along with voids in a second mold layer for optical coupling, allowing light transmission through dielectric material above the optical interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the photonic integrated circuit is mounted on a substrate with a semiconductor chip using 2.5D architecture, then the optical fiber interface is maintained, but high-density short-distance interconnection is not achieved
Solution Approach 1:
The patent transitions from planar 2.5D mounting to a three-dimensional stacked architecture where the photonic integrated circuit is positioned directly above the semiconductor chip in the vertical dimension. This vertical integration enables short-distance interconnection while maintaining optical fiber accessibility through side-mounted optical couplings on the package housing.
Solution Approach 2:
The photonic integrated circuit is nested within the package housing directly above the semiconductor chip, with optical couplings nested within voids in the mold layer. This nested arrangement allows both components to coexist in a compact volume while maintaining their respective functions for electrical and optical interconnection.
2Productivity
If tighter integration of photonic integrated circuit and semiconductor chip is implemented, then interconnection density improves, but accessibility for optical fiber coupling is lost
Solution Approach 1:
The package structure is segmented into distinct functional zones: the semiconductor chip at the bottom, the photonic integrated circuit above it, and optical couplings positioned in separate voids within the mold layer. This segmentation allows each component to be optimally positioned for its function while maintaining overall compact integration.
Solution Approach 2:
The mold layer with integrated voids acts as an intermediary structure that simultaneously provides mechanical support for the stacked components and creates accessible pathways for optical fiber coupling. The voids serve as intermediary spaces that reconcile the conflicting requirements of tight integration and optical accessibility.
3Reliability
If the photonic integrated circuit is encased in mold layers, then protection and integration are improved, but optical transmission path is blocked
Solution Approach 1:
Voids are extracted from the mold layer at strategic positions to create optical transmission pathways. These voids remove the obstructive mold material only where needed for optical coupling, while the rest of the mold layer remains intact to provide protection and structural support for the integrated components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enables high-density, short-distance electrical connections between photonic integrated circuits and semiconductor chips while allowing optical fiber coupling, enhancing performance and efficiency in applications such as data centers and AI systems.
Implementation Method 1
allows light transmission through dielectric material above the optical interface
Data Source
AI summary
A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.