Fan-Out Multi-Chip Stacked Package Reducing Wire Sweeping
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Solution Overview
Problem
Conventional multi-chip stacked packages have a thick profile due to substrate and encapsulation thickness, which can lead to wire sweeping and electrical shorts during encapsulant deposition, especially with longer bonding wires.
Innovation Solution
A fan out multi-chip stacked package design featuring stacked chips with exposed electrodes, flip-chip bumps, and a redistribution layer, where dummy flip chips are used to form a planar surface after encapsulation, reducing package thickness and eliminating the need for conventional wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-chip stacked packages use substrate and encapsulation thickness to protect chips, then chip protection is improved, but package thickness increases
Solution Approach 1:
The patent removes the substrate from the package structure, retaining only the essential encapsulation layer. This extraction of the substrate eliminates its thickness contribution to the overall package height while preserving the protective function through the encapsulation material that directly bonds to the chip back surfaces.
Solution Approach 2:
Instead of placing chips on a substrate and then encapsulating, the patent inverts the approach by directly encapsulating the stacked chips without a substrate intermediary. The encapsulation becomes the primary structural and protective element rather than an add-on layer.
2Reliability
If conventional packages use longer and higher bonding wires for electrical connection, then electrical connectivity is improved, but wire sweeping risk increases
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a direct encapsulation-based electrical connection system. The encapsulation material itself provides the electrical pathways through conductive traces embedded within it, eliminating the need for separate mechanical wire bonds that are susceptible to sweeping during deposition.
3Reliability
If conventional packages use wire bonding process for electrical connection, then electrical connectivity is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the encapsulation process with the electrical connection formation process. The conductive traces are integrated into the encapsulation material during a single deposition step, combining what were previously separate operations (wire bonding plus encapsulation) into one unified manufacturing step, thereby reducing overall process complexity.
Data Source
AI summary
A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. A plurality of flip-chip bumps of a dummy flip chip are coupled to the electrodes of the chips. An encapsulant encapsulates the chip stacked assembly and the flip-chip bumps. The encapsulant has a planar surface. The flip-chip bumps have a plurality of bonding surfaces exposed from and coplanar to the planar surface. A redistribution layer is disposed on the planar surface and includes a plurality of fan out circuits electrically connected the bonding surfaces of the flip-chip bumps. Thus, the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping.