Fan-out Semiconductor Package with Multiple Via Shape
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Solution Overview
Problem
The existing fan-in semiconductor packages face challenges in accommodating a large number of I/O terminals and compact size requirements, leading to spatial limitations and difficulties in direct mounting on electronic device mainboards, necessitating the use of interposer substrates for redistribution of connection pads.
Innovation Solution
A fan-out semiconductor package design with a connection member featuring an insulating layer, redistribution layer, and conductive vias, where the conductive vias have a multiple via shape with integrated sub-vias, allowing for stable electrical connections and redistribution of I/O terminals outside the semiconductor chip, enabling direct mounting on mainboards without interposer substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fan-in semiconductor package structure is used, then the semiconductor chip can be packaged, but the package size becomes large and direct mounting on mainboard is difficult
Solution Approach 1:
The patent transitions from fan-in configuration to fan-out configuration, where connection terminals are redistributed from underneath the chip to the outer perimeter of the package. This dimensional reorganization allows the package to be mounted directly on mainboards without requiring an interposer substrate, effectively solving the mounting ease problem while maintaining compact size.
Solution Approach 2:
The connection terminals are segmented and redistributed to different locations on the package substrate. Instead of having all terminals concentrated under the chip, they are divided and arranged along the perimeter, enabling direct mounting while accommodating multiple I/O terminals.
2Adaptability or versatility
If the number of I/O terminals is increased, then functionality is improved, but the package area becomes larger
Solution Approach 1:
The connection terminals are arranged in a fan-out pattern around the perimeter of the package substrate rather than being concentrated in a small area under the chip. This peripheral arrangement allows a high density of I/O terminals to be accommodated along the edges, increasing functionality without significantly increasing the overall package area.
Solution Approach 2:
Different regions of the package substrate serve different functions: the center region accommodates the semiconductor chip, while the peripheral regions are optimized for high-density terminal arrangements. This localized optimization allows maximum I/O terminal count within minimal package area.
3Volume of moving object
If connection terminals are redistributed outwardly, then compact size is achieved, but electrical connection stability becomes challenging
Solution Approach 1:
The redistribution of connection terminals to the outer perimeter creates longer trace paths that require careful impedance control and signal integrity management. The patent addresses this by optimizing the trace routing and termination strategies to maintain electrical connection stability despite the extended paths.
Solution Approach 2:
The package substrate acts as an intermediary between the semiconductor chip and the external circuitry. It provides controlled impedance traces, proper signal termination, and stable electrical connections, mediating the electrical interface between the chip and the redistributed peripheral terminals.
Data Source
AI summary
A fan-out semiconductor package includes a connection member including an insulating layer, a redistribution layer, and conductive vias penetrating through the insulating layer and connected to the redistribution layer, and a semiconductor chip and a passive chip disposed on the connection member and electrically connected to the redistribution layer. A conductive via connected to the passive element among the conductive vias has a multiple via shape in which a plurality of sub-vias, a width of each sub-via is decreased in a thickness direction, and end portions of the plurality of sub-vias are integrated with each other.