Fan-Out Semiconductor Package Active Surface Passive Component Mounting

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Fan-out semiconductor packages face limitations in securing a sufficient number of connection terminals, such as solder balls, when incorporating passive components, which also increases the signal distance between the semiconductor chip and the passive component, making it difficult to achieve thinness and compactness.

Innovation Solution

A fan-out semiconductor package design where a passive component is attached to the active surface of a semiconductor chip with connection pads, and a redistribution layer is used to electrically connect the passive component to the connection pads, allowing for a reduction in signal distance and enabling thinner, more compact packaging by redistributing connection terminals outwardly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If passive components are mounted on the lower surface of a fan-out semiconductor package, then the package characteristics are improved, but the space for solder balls is limited

Engineering Contradiction:
Improvepackage characteristicsVSAvoidspace for solder balls
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from mounting passive components on the lower surface (2D plane) to mounting them on the active surface (different dimension/orientation). This dimensional change allows solder balls to be arranged in a standardized ball layout on the lower surface without obstruction, while passive components are positioned on the active surface where they can be electrically connected through redistribution layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If passive components are mounted on the lower surface of a fan-out semiconductor package, then the package characteristics are improved, but the signal distance between semiconductor chip and passive component increases

Engineering Contradiction:
Improvepackage characteristicsVSAvoidsignal distance
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent introduces redistribution layers as intermediary structures that enable direct electrical connection between the semiconductor chip and passive components mounted on the active surface. These redistribution layers act as mediators, allowing signals to travel a shorter distance through the package structure rather than requiring long traces on the lower surface.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If passive components are mounted on the lower surface of a fan-out semiconductor package, then the package characteristics are improved, but achieving thinness becomes difficult

Engineering Contradiction:
Improvepackage characteristicsVSAvoidpackage thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent merges the mounting location of passive components with the active surface of the semiconductor chip, combining multiple functions into a single spatial region. This consolidation eliminates the need for separate lower surface mounting areas and reduces overall package thickness, while maintaining all necessary electrical connections through integrated redistribution layers.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10177100B2Fan-out semiconductor package
Publication Date: 2019.01.08 SAMSUNG ELECTRONICS CO LTD
  • US10177100B2 patent drawing
  • US10177100B2 patent drawing
  • US10177100B2 patent drawing

AI summary

A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole of the first connection member, the semiconductor chip including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a passive component attached to the active surface of the semiconductor chip, an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, the first connection member and the second connection member each including at least one redistribution layer electrically connected to the connection pads of the semiconductor chip, and the passive component being electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.