Fan-Out Package Structure With Azimuthal Die Offset Against Cracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Mechanical stress during the stacking and dicing processes in fan-out wafer level packages leads to undesirable cracking, reducing the yield of devices.
Innovation Solution
The orientation of primary and complementary semiconductor dies is azimuthally offset from the horizontal directions of the sidewalls, aligning major crystallographic directions of the carrier wafer and dies to minimize stress concentration, and the use of molding compounds to reinforce the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stacking and dicing processes are used, then manufacturing efficiency is maintained, but mechanical stress causes cracking and reduces device yield
Solution Approach 1:
The patent applies asymmetry by orienting semiconductor dies at non-traditional angles (e.g., 45 degrees) relative to the carrier wafer's major crystallographic directions. This asymmetric orientation prevents alignment of stress concentrations with crystallographic planes, thereby reducing mechanical stress cracking during stacking and dicing processes while maintaining manufacturing efficiency
Solution Approach 2:
The patent introduces molding compound as an intermediary material that encapsulates the semiconductor dies and carrier wafer assembly. This intermediary provides mechanical support and stress distribution, reducing the direct transmission of mechanical stress that would otherwise cause cracking at die-carrier interfaces during handling and dicing
2Strength
If die orientation is azimuthally offset to reduce stress, then cracking is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent changes the orientation parameter of die placement from conventional orthogonal alignment to azimuthally offset angles (such as 45 degrees). This parameter change optimizes mechanical strength by reducing stress concentration while the offset angle is selected to balance manufacturing complexity, allowing standard equipment to handle the process with minimal additional complexity
Data Source
AI summary
An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.


