Fan-Out Package Protective Layer for Reliable Chip Dicing

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Solution Overview

Problem

Current fan-out package technology faces challenges in manufacturing process reliability and yield, necessitating improvements for miniaturized, high-performance, and cost-effective electronic devices.

Innovation Solution

The electronic device comprises a chip unit, a first insulating layer, a second insulating layer, and a protective layer, with the second insulating layer overlapping the chip unit after a dicing process, and a manufacturing method involving the formation of these layers to enhance structural strength and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fan-out package technology is used to extend wiring from the die area, then the package structure achieves high integration, but manufacturing process reliability and yield deteriorate

Engineering Contradiction:

Improvepackage structure integrationVSAvoidmanufacturing process reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective layer on the chip unit before the dicing process. This protective layer is formed in advance to prevent damage to the chip unit and insulating layers during subsequent manufacturing steps, thereby improving manufacturing reliability while maintaining the fan-out package structure integration.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by introducing a protective layer that acts as a cushioning barrier before the dicing process. This protective layer prevents direct mechanical damage to the chip unit and insulating layers during cutting, thereby protecting the manufacturing process reliability while preserving the integrated package structure.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Volume of moving object

If chip size is scaled down for miniaturization, then electronic device size is reduced, but manufacturing precision and reliability deteriorate

Engineering Contradiction:

Improveelectronic device sizeVSAvoidchip manufacturing precision

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the protective layer before dicing, which provides a protective barrier that prevents damage to the scaled-down chip unit during the dicing process. This allows miniaturization to proceed while maintaining manufacturing precision through the protective barrier.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses a protective layer (thin film) that covers and protects the chip unit and insulating layers. This thin film structure provides mechanical protection during dicing and handling, enabling precise manufacturing of miniaturized chips while maintaining reliability through the protective barrier.

Inventive Principle:

Principle #30Flexible shells and thin films

3Productivity

If dicing process is performed to separate chip units, then individual electronic units are formed, but damage to chip unit and insulating layers occurs

Engineering Contradiction:

Improveelectronic unit productionVSAvoidchip unit integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming the protective layer before the dicing process. This protective layer is prepared in advance to shield the chip unit and insulating layers from damage during the dicing operation, thereby enabling high productivity while maintaining chip unit integrity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by introducing a protective layer that acts as a cushioning barrier before dicing. This protective layer absorbs mechanical stresses during the cutting process, preventing damage to the chip unit and insulating layers while maintaining productivity through efficient mass production.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

4Reliability

If multiple insulating layers are formed to improve electrical properties, then circuit layout area is expanded, but device complexity increases

Engineering Contradiction:

Improveelectrical propertiesVSAvoidinsulating layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the protective layer to serve multiple functions: it protects the chip unit and insulating layers during dicing, provides electrical insulation, and supports subsequent circuit layer formation. This multi-functionality improves electrical properties while minimizing the increase in device complexity by using a single versatile layer rather than multiple specialized layers.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230402393A1Electronic device and manufacturing method thereof

Publication Date: 2023.12.14 INNOLUX CORP

AI summary

An electronic device is provided. The electronic device includes an electronic unit, a protective layer, and a circuit layer. The electronic unit includes a chip unit, a first insulating layer, and a second insulating layer. The first insulating layer is disposed on the chip unit, and the second insulating layer is disposed on the first insulating layer. The second insulating layer has a first side. The first side overlaps the chip unit along the normal direction of the electronic unit. The protective layer surrounds the electronic unit, and the circuit layer electrically connects the electronic unit.