Fan-out Semiconductor Package with Coreless Substrate
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Solution Overview
Problem
Current fan-in semiconductor packages face challenges in miniaturization and rigidity due to spatial limitations and the need for separate interposer substrates, which complicates the manufacturing process and limits thinness and design flexibility.
Innovation Solution
A fan-out semiconductor package design incorporating a first connection member with redistribution layers and a second encapsulant without a core material, utilizing insulating resin and inorganic fillers for enhanced rigidity and thinness, along with a passivation layer to control warpage and improve board-level reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fan-in semiconductor package is used, then the package can be manufactured with conventional processes, but the package size cannot be reduced further and rigidity is insufficient
Solution Approach 1:
The patent transitions from fan-in packaging to fan-out packaging, redistributing connection terminals from underneath the chip to the front surface. This dimensional reorganization allows the package to achieve better rigidity through the substrate structure while maintaining compact size by utilizing the surface area of the substrate for terminal arrangement.
Solution Approach 2:
The patent employs a substrate composed of multiple layers including a core layer, first encapsulant layer, and second encapsulant layer. This composite structure provides enhanced rigidity and mechanical strength while allowing for thin overall package design. The different materials serve specific functions: core layer for structural support, first encapsulant for chip protection, and second encapsulant for additional reinforcement and terminal support.
2Reliability
If separate interposer substrates and reinforcing layers are added, then rigidity and electrical connection are improved, but the manufacturing process becomes complex and the package thickness increases
Solution Approach 1:
The patent integrates the interposer substrate function directly into the main substrate structure by forming the substrate as a single integrated component with multiple functional layers. The redistribution layers are formed directly on the substrate, eliminating the need for separate interposer substrates. This merging of functions simplifies the manufacturing process while maintaining board-level reliability through the well-controlled substrate structure.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support and rigidity, enables electrical redistribution through integrated redistribution layers, offers thermal management pathways, and supports the connection terminals. This multi-functionality eliminates the need for separate specialized components, reducing manufacturing complexity while achieving comprehensive performance.
3Volume of moving object
If the package is thinned to reduce size, then compactness is achieved, but rigidity and warpage control become problematic
Solution Approach 1:
The patent uses a multi-layer composite substrate structure with a core layer sandwiched between first and second encapsulant layers. This composite construction provides inherent rigidity and dimensional stability even in thin packages. The different materials have complementary properties that work together to resist warping while maintaining overall thinness. The core layer provides structural backbone, while the encapsulant layers add flexibility and protection.
Solution Approach 2:
The patent carefully controls the thickness parameters of each substrate layer to achieve the optimal balance between overall package thinness and local rigidity. By adjusting the thickness of the core layer, first encapsulant layer, and second encapsulant layer independently, the design achieves warpage control in critical areas while maintaining compact overall dimensions. The thickness ratios are optimized to distribute stress evenly and prevent warping.
Data Source
AI summary
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip, a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip. The fan-out semiconductor package may have excellent rigidity, may be thinned, and may be manufactured in a simplified process.