Fan-Out Package Post Structure for Upper Substrate Crack Suppression
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Solution Overview
Problem
As semiconductor chip sizes decrease, it becomes challenging to bond the required number of bumps while handling and testing the chip, and the reduced size makes it difficult to maintain alignment with international standards, leading to potential cracking issues in the upper substrate.
Innovation Solution
A fan-out package design is implemented, featuring a lower substrate with upper pads, posts, and an upper substrate with lower pads, where the posts and pads form an 'I' shape, and a mold layer is used to connect them, with the upper pads and lower pads having different diameters to suppress cracking and facilitate bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the semiconductor chip size is reduced to increase integration, then the number of bumps that can be bonded increases, but the chip becomes difficult to handle and test
Solution Approach 1:
The invention divides the chip structure into two separate substrates (first substrate and second substrate) connected by bumps. This segmentation allows each substrate to be optimized independently - the first substrate can have high integration with many bumps while the second substrate provides a larger, more manageable interface for handling and testing, thus resolving the contradiction between increasing bump quantity and maintaining ease of operation.
Solution Approach 2:
The invention transitions from a single-plane chip structure to a three-dimensional stacked structure with two substrates connected vertically by bumps. This dimensional change allows the bump array to be distributed across multiple layers, increasing the effective number of bumps while maintaining manageable dimensions for handling and testing at each level.
2Quantity of substance
If the semiconductor chip size is reduced, then integration increases, but alignment with international standards and structural integrity deteriorate
Solution Approach 1:
By segmenting the chip into two substrates, the invention allows each substrate to maintain larger dimensions that comply with international standards while achieving high overall integration through the stacked configuration. The alignment requirements are distributed across two separate bonding interfaces rather than concentrated on a single small chip, improving manufacturing precision.
Solution Approach 2:
The vertical stacking approach moves the integration challenge from the two-dimensional plane to the third dimension, allowing each substrate to maintain standard-compliant sizes while achieving high integration through the vertical arrangement of multiple bump arrays across different levels.
3Reliability
If posts with smaller diameter than pads are used, then cracking of the upper substrate is suppressed, but manufacturing complexity increases
Solution Approach 1:
The invention applies different diameters to different components locally - the posts have a first diameter while the pads have a second diameter greater than the post diameter. This local differentiation creates a stepped configuration that redistributes stress away from critical interfaces, suppressing cracks in the upper substrate while maintaining overall manufacturing feasibility through a systematic design approach.
Data Source
AI summary
Disclosed are packages and their fabrication methods. The package includes: a lower substrate with an upper pad; a lower chip on the lower substrate; a mold layer on the lower chip and the lower substrate; a post extending through the mold layer and provided on the upper pad around the lower chip, the post having a diameter less than a diameter of the upper pad; and an upper substrate on the post and the mold layer, the upper substrate including a lower pad having a diameter greater than the diameter of the post.