Wafer-Level Fanout Package for Precise Silicon Photonics Fiber Attach
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Solution Overview
Problem
The silicon photonics industry faces challenges in wafer-level testing and packaging of edge-coupled silicon photonics, particularly in efficiently coupling optical fibers to chips for light transmission, due to difficulties in concurrent electrical and optical probing and the need for precise alignment of optical grating couplers.
Innovation Solution
A silicon photonics chip package assembly is developed, featuring a mold compound structure around the chip, a redistribution layer with conductive interconnects, and an optical fiber coupling region with v-groove structures for precise alignment of optical fibers, allowing for wafer-level processing and packaging that includes optical testing and fiber coupling, while maintaining the integrity of the chip's optical waveguides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level processing is used for silicon photonics packaging, then productivity is improved, but manufacturing precision deteriorates due to difficulties in concurrent electrical and optical probing
Solution Approach 1:
The packaging process is divided into separate electrical testing (using probe cards on pad structures) and optical fiber coupling steps, allowing wafer-level electrical testing to be performed with high productivity while optical fiber alignment is performed separately with high precision using v-groove structures
Solution Approach 2:
V-groove structures are introduced as intermediary alignment features that mechanically guide optical fibers into precise alignment with waveguides, eliminating the need for complex active alignment processes and enabling high-precision coupling at wafer-level
2Adaptability or versatility
If optical grating couplers are used for fiber coupling, then adaptability is improved, but device complexity increases due to the need for precise alignment
Solution Approach 1:
The v-groove structures are self-aligning features that passively guide optical fibers into the correct position through mechanical interference, eliminating the need for complex active alignment mechanisms and reducing device complexity while maintaining coupling adaptability
3Manufacturing precision
If conventional packaging methods are used, then manufacturing precision is maintained, but productivity deteriorates due to inability to perform wafer-level testing
Solution Approach 1:
Electrical pad structures and optical waveguides are pre-configured on the wafer before dicing, allowing electrical testing to be performed at wafer-level using probe cards, thereby maintaining waveguide integrity through reduced handling while significantly increasing testing and packaging throughput
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient wafer-level testing and packaging of silicon photonics chips, facilitating the alignment and coupling of optical fibers with the chips, thereby enhancing the transmission of light and improving the overall performance of silicon photonics devices.
Implementation Method 1
an optical fiber coupling region formed along a portion of the first side of the silicon photonics chip... at least one optical fiber connected to the optical fiber coupling region in optical alignment with the at least one optical waveguide
Data Source
AI summary
A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.