Fan-Out Semiconductor Package with Dummy Substrate Heat Spreader
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Solution Overview
Problem
Fan-out wafer level packages experience warpage and limited heat dissipation due to asymmetric structures and the thickness of semiconductor chips, which is constrained by the height of copper posts in the mold via.
Innovation Solution
Incorporating a dummy substrate layer that covers the fan-out region to reduce warpage and enhance heat dissipation by acting as a heat spreader, with through electrodes and dummy through electrodes to effectively dissipate heat from the semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a relatively thick semiconductor chip is mounted on the lower redistribution wiring layer to improve heat dissipation characteristics, then heat dissipation is improved, but warpage occurs in corner areas of the package due to asymmetric structure
Solution Approach 1:
The patent introduces a dummy substrate layer that is disposed only in corner areas of the package, creating an asymmetric structure that specifically addresses warpage in corner regions without interfering with the heat dissipation function of the thick semiconductor chip. This localized asymmetric addition balances the stress distribution in corner areas while preserving the overall asymmetric heat dissipation path.
Solution Approach 2:
The dummy substrate layer is selectively placed only in corner areas where warpage occurs, rather than uniformly across the entire package. This local quality approach allows the corner areas to have different structural properties (additional dummy substrate) compared to the central area, addressing the specific warpage problem in corners while maintaining the heat dissipation effectiveness in the central region.
2Temperature
If the thickness of the semiconductor chip is increased to improve heat dissipation characteristics, then heat dissipation is improved, but the thickness is limited by the height of copper post in mold via
Solution Approach 1:
The dummy substrate layer acts as an intermediary structure that provides additional heat dissipation pathways through its own thermal conduction properties and by enabling extended chip thickness beyond the copper post limitation. The dummy substrate serves as a mediator between the semiconductor chip and the package substrate, creating alternative heat flow paths that are not constrained by the copper post height.
3Stability of the object's composition
If a dummy substrate layer is added to reduce warpage and enhance heat dissipation, then warpage and heat dissipation are improved, but device complexity increases
Solution Approach 1:
The package structure is segmented into functional zones: corner areas receive the dummy substrate layer for warpage control, while the central area maintains the original structure for heat dissipation. This segmentation allows the dummy substrate to be added only where needed, minimizing the increase in overall device complexity while achieving the desired warpage reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dummy substrate layer improves the warpage of the edge region and enhances heat dissipation characteristics by spreading heat and providing heat dissipation passages, addressing the limitations of existing fan-out wafer level packages.
Implementation Method 1
The dummy substrate layer may serve as a heat spreader that spreads heat from the semiconductor chip
Implementation Method 2
the dummy through electrodes may serve as heat dissipation passages to effectively dissipate heat from the semiconductor chip to the outside
Data Source
AI summary
A semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings, at least one semiconductor chip disposed on, and electrically connected to, the lower redistribution wiring layer, a sealing member disposed on the lower redistribution wiring layer and having a plurality of through vias that penetrate the sealing member and are electrically connected to the lower redistribution wirings, a dummy substrate layer stacked on the sealing member and the at least one semiconductor chip and having a plurality of through electrodes that penetrate the dummy substrate layer and are electrically connected to the plurality of through vias, and an upper redistribution wiring layer disposed on the dummy substrate layer and having upper redistribution wirings that are electrically connected to the plurality of through electrodes.