Fan-Out Semiconductor Package I/O Redistribution and Grinding Reference
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Solution Overview
Problem
Current fan-in semiconductor packages face spatial limitations and challenges in mounting semiconductor chips with a large number of I/O terminals or compact sizes directly on electronic device mainboards due to the need for all I/O terminals to be disposed inside the chip, which restricts their application and requires additional packaging steps like BGA substrates for mounting.
Innovation Solution
The fan-out semiconductor package design redistributes I/O terminals outwardly of the semiconductor chip using a connection member, allowing for a standardized ball layout and direct mounting on the mainboard without a separate BGA substrate, featuring a frame with recessed portions and dummy structures with sloped side surfaces to facilitate grinding and residual thickness measurement during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fan-in semiconductor package design is used with all I/O terminals disposed inside the chip, then the chip structure is compact, but the package size cannot be reduced further and additional BGA substrate is required for mounting
Solution Approach 1:
The patent transitions from a fan-in configuration where all I/O terminals are disposed inside the chip to a fan-out configuration where I/O terminals are redistributed outwardly of the chip. This dimensional redistribution allows the package to achieve both compact size and direct mounting capability by utilizing the space around the chip rather than confining all connections to the chip surface.
Solution Approach 2:
The patent segments the I/O terminals into two groups: those connected to the chip and those redistributed outwardly. This segmentation is achieved through a connection member with a redistribution layer that separates the I/O terminal functions, allowing some terminals to remain close to the chip while others are positioned outward for direct mounting applications.
2Manufacturing precision
If grinding process is used to measure residual thickness of interconnect structure, then manufacturing precision can be achieved, but expensive measuring devices and complex settings are required
Solution Approach 1:
The patent introduces a dummy structure as an intermediary reference object during the grinding process. This dummy structure, positioned adjacent to the interconnect structure, serves as a reference for measuring the residual thickness of the interconnect structure. By using this intermediary reference, the measurement can be performed with simpler equipment and procedures while maintaining manufacturing precision.
Solution Approach 2:
The dummy structure is essentially a copy or replica of the interconnect structure in terms of its grinding characteristics and material properties. This copying allows the residual thickness of the actual interconnect structure to be inferred from the dummy structure, simplifying the measurement process while maintaining accuracy.
3Volume of moving object
If I/O terminals are redistributed outwardly of the semiconductor chip, then package size can be reduced and direct mounting is enabled, but the wiring structure becomes more complex
Solution Approach 1:
The patent merges the chip, connection member with redistribution layer, and outwardly positioned I/O terminals into a single integrated fan-out package structure. This merging eliminates the need for separate BGA substrates and reduces the overall package volume while managing wiring complexity through integrated design.
Solution Approach 2:
The patent utilizes three-dimensional spatial arrangement by redistributing I/O terminals outwardly of the chip in the fan-out configuration. This dimensional change allows for more efficient use of package space and enables direct mounting capabilities without proportionally increasing wiring complexity, as the redistribution follows a systematic pattern rather than random placement.
Data Source
AI summary
A fan-out semiconductor package includes a frame comprising wiring layers, and a dummy layer, and having a recessed portion on a bottom surface on which a stopper layer is disposed; a semiconductor chip disposed in the recessed portion such that an inactive surface opposes the stopper layer; a first interconnect structure disposed on the connection pad; a second interconnect structure disposed on the outermost wiring layer; a dummy structure disposed on the dummy layer; an encapsulant encapsulating at least portions of the frame, the semiconductor chip, the first interconnect structure, the second interconnect structure, and the dummy structure, and filling at least a portion of the recessed portion; and a connection member disposed on the frame and an active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to first and second metal bumps. The dummy structure has sloped side surfaces.