Fan-out Package Lateral Interconnects for Reduced Size
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size of electronic components and packaging them efficiently, as existing methods struggle to accommodate the increasing integration density of components within smaller areas while maintaining cost-effectiveness and structural integrity.
Innovation Solution
A fan-out package structure is developed, where chips are adhered to a carrier substrate, laterally encapsulated with a molding compound, and interconnected using multiple dielectric and metallization layers, allowing for efficient electrical coupling and reduced package size through precise metallization layer formation and patterning, enabling fine-pitch packaging and cost reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used, then structural integrity is maintained, but package size cannot be reduced sufficiently
Solution Approach 1:
The patent transitions from traditional vertical stacking to lateral fan-out interconnection, spreading electrical connections horizontally across the substrate rather than vertically through the package. This dimensional change enables smaller package footprints while maintaining structural integrity through distributed lateral connections.
Solution Approach 2:
The package structure is divided into distinct functional layers including die, underfill, substrate, and molding compound, each serving specific mechanical and electrical functions. This segmentation allows optimization of each layer for its specific purpose while maintaining overall structural integrity.
2Productivity
If integration density is increased, then component functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The substrate serves multiple functions simultaneously: mechanical support for the die, electrical interconnection platform, and thermal management pathway. This multi-functionality reduces the need for additional specialized components, thereby simplifying the manufacturing process despite high integration density.
Solution Approach 2:
The die is pre-attached to the substrate and pre-wired with lateral interconnections before final package assembly. This preliminary action allows subsequent manufacturing steps to focus on encapsulation and testing, reducing overall manufacturing complexity.
3Area of stationary object
If package size is reduced, then space utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The substrate acts as an intermediary platform with predefined alignment features and trace routing that guides the placement and connection processes. This intermediary structure provides mechanical references and electrical pathways that reduce the precision demands on direct die-to-package alignment.
Solution Approach 2:
Standardized substrate designs with replicated alignment features and trace patterns are used across multiple packages. This copying approach allows manufacturing equipment to use the same alignment protocols and positioning methods, reducing precision requirements through repeatability.
Data Source
AI summary
An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.