Fan-Out Panel Level Package Misalignment Compensation
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Solution Overview
Problem
The challenge in the semiconductor industry is the difficulty in adjusting the number of solder balls on reduced-sized semiconductor chips due to fixed distances, leading to misalignment and interconnection failures between fan-out substrates and dies, which complicates handling and testing.
Innovation Solution
A method for fabricating a fan-out panel level package involves detecting the positions of dies on a fan-out substrate, forming interconnection lines with specific extensions to connect misaligned dies to the substrate, and using a patterning process to create contact holes and connect substrate electrodes to die pad electrodes, thereby minimizing alignment-related defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chip sizes are reduced, then integration density is improved, but alignment precision between dies and fan-out substrate deteriorates
Solution Approach 1:
The patent applies preliminary action by forming an extended portion of the interconnection line that protrudes beyond the die edge before the die is fully positioned on the fan-out substrate. This extended portion is created in advance during the interconnection line formation process, allowing it to serve as a positioning guide that compensates for potential misalignment when the die is later placed on the substrate.
2Device complexity
If interconnection lines are formed directly between substrate and die, then device complexity is reduced, but reliability deteriorates due to misalignment
Solution Approach 1:
The patent introduces an extended portion as an intermediary element between the interconnection line and the die. This extended portion protrudes beyond the die edge and serves as a mediator that facilitates reliable electrical connection even when there is misalignment between the die and the fan-out substrate. The intermediary structure absorbs the misalignment stress and ensures continuous electrical connectivity.
Data Source
AI summary
A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with respect to the fan-out substrate, and forming interconnection lines. At least one of the interconnection lines includes a first portion extending from the fan-out substrate to a target position on the cavity disposed between the fan-out substrate and one of the dies the one of the dies disposed at a detected position different from the target position, and a second portion extending from the one die to the fan-out substrate.