Fan-Out Package Pin Exposure for Size Reduction
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Solution Overview
Problem
Current fan-out wafer-level package technologies face challenges with high packaging costs, large line width and distance, and complex process implementation, which hinder chip miniaturization and increase material consumption.
Innovation Solution
A chip structure comprising a fan-out unit with integrated dies, a first substrate with a re-distribution layer, and a molding body that wraps the pins and substrate, allowing direct electrical connection to the chip periphery without an intermediary substrate, reducing overall size and process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pins on a die are electrically connected to the periphery of the package structure through a substrate, then electrical connection is achieved, but the overall size of the package structure becomes relatively large
Solution Approach 1:
The patent extracts the substrate from the electrical connection path by allowing pins to directly contact the periphery of the package structure. The molding body is configured to expose pin arrays at its periphery, eliminating the need for substrate-based electrical connection and thereby reducing the overall package size while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent transitions from a planar substrate-based connection approach to a three-dimensional molding body structure where pins extend through and are exposed at the periphery. This dimensional change allows electrical connections to be made directly at the package edges without requiring a large substrate area, thus reducing the overall footprint.
2Productivity
If existing fan-out wafer-level package structure is used, then I/O pins can be led out on a wafer, but the package area and material consumption increase
Solution Approach 1:
The patent merges the functions of the substrate and the molding body into a single integrated structure. The molding body both encapsulates the dies and provides the structural framework for I/O pin lead-out, eliminating the need for a separate substrate and reducing overall package area while maintaining the fan-out capability.
Solution Approach 2:
The molding body is designed to perform multiple functions simultaneously: it provides mechanical support, electrical insulation, environmental protection, and serves as the structural basis for I/O pin lead-out. This multi-functionality eliminates the need for additional substrate layers, reducing package area and material consumption.
3Reliability
If substrate is used for electrical connection, then interconnection is achieved, but the number of components and process complexity increase
Solution Approach 1:
The patent combines the substrate function with the molding body, creating a single integrated component rather than separate substrate and molding body layers. This merging reduces the number of components and simplifies the manufacturing process while maintaining reliable interconnection through the exposed pin arrays at the periphery.
Data Source
AI summary
A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.