Fan-Out Package Alignment Marks for Precise RDL Overlay

Solution Overview

Problem

Integrated fan-out packages face challenges related to compactness, alignment accuracy, and overlay precision due to the miniaturization of electronic components and the need for smaller packages.

Innovation Solution

The method involves forming semiconductor dies with conductive posts and alignment marks, which are then encapsulated and connected through a redistribution layer. This process enhances alignment accuracy and overlay precision by using stripe patterns in the alignment marks and auxiliary alignment marks in the redistribution layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If integrated fan-out packages are miniaturized to achieve compactness, then package size is reduced, but alignment accuracy and overlay precision deteriorate

Engineering Contradiction:

Improvepackage sizeVSAvoidalignment accuracy

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The alignment mark is divided into multiple stripe patterns arranged in specific geometric configurations. This segmentation allows the alignment system to detect positional deviations more accurately by analyzing the relative positions of multiple stripes, thereby maintaining high alignment accuracy even in miniaturized packages

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The alignment marks utilize two-dimensional stripe patterns with specific spatial arrangements rather than simple one-dimensional marks. This dimensional enhancement provides more information for alignment detection, improving overlay precision while accommodating smaller package dimensions

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If integrated fan-out packages are miniaturized to achieve compactness, then package size is reduced, but overlay precision deteriorates

Engineering Contradiction:

Improvepackage sizeVSAvoidoverlay precision

Core Design Contradiction:

Volume of moving objectVSMeasurement precision

Solution Approach 1:

The alignment mark is divided into multiple stripe patterns arranged in specific geometric configurations. This segmentation allows the alignment system to detect positional deviations more accurately by analyzing the relative positions of multiple stripes, thereby maintaining high alignment accuracy even in miniaturized packages

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The alignment marks utilize two-dimensional stripe patterns with specific spatial arrangements rather than simple one-dimensional marks. This dimensional enhancement provides more information for alignment detection, improving overlay precision while accommodating smaller package dimensions

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If alignment marks with stripe patterns are used to improve alignment accuracy, then alignment precision is enhanced, but manufacturing complexity increases

Engineering Contradiction:

Improvealignment precisionVSAvoidalignment mark structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The stripe pattern alignment marks serve multiple functions: they provide alignment references for different layers, enable detection of both lateral and rotational misalignments, and can be integrated with the existing passivation layer structure. This multi-functionality reduces the need for additional separate alignment features, offsetting the increased pattern complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12211802B2Package structure and method of fabricating the same

Publication Date: 2025.01.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.