Fan-Out Package Recess Stopper Layer Thickness Control

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Solution Overview

Problem

The existing fan-out semiconductor package process faces challenges with increased defects, investment costs, and process costs due to the sequential addition of a redistribution layer on the backside, which affects productivity and quality, particularly in forming a blind recess portion without impacting the package thickness or causing warpage.

Innovation Solution

A fan-out semiconductor package design that includes a frame with a blind recess portion and a stopper layer thicker than the wiring layers, allowing for easier application of a wiring layer on the backside, improved productivity, and maintained package thickness, by forming the recess portion before embedding the semiconductor chip and adjusting the stopper layer thickness independently of the wiring layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a redistribution layer on the backside is sequentially added after front side redistribution layer forming process is completed, then the number of I/Os can be increased, but defects increase, investment costs increase, and process costs increase

Engineering Contradiction:
Improvenumber of I/OsVSAvoiddefects
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming the blind recess portion and stopper layer on the frame before mounting the semiconductor chip. This allows the backside redistribution layer to be formed simultaneously with the front side process rather than sequentially, reducing defects and process costs while enabling increased I/Os

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If a redistribution layer on the backside is sequentially added after front side redistribution layer forming process is completed, then the number of I/Os can be increased, but investment costs increase and process costs increase

Engineering Contradiction:
Improvenumber of I/OsVSAvoidinvestment costs and process costs
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The blind recess portion and stopper layer are prepared in advance on the frame before chip mounting, enabling simultaneous formation of backside redistribution layer with front side processes. This eliminates the need for separate backside processing equipment and reduces process costs while increasing I/O capacity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the front side and backside redistribution layer formation processes into a single simultaneous operation. The frame structure with pre-formed blind recess portions allows both sides to be processed together, reducing investment costs and simplifying manufacturing

Inventive Principle:
Principle #5Merging (Combining)

3Length of stationary object

If the thickness of wiring layers is reduced to maintain package thickness, then the overall package thickness is maintained, but the quality of blind recess portion formation is affected

Engineering Contradiction:
Improvepackage thicknessVSAvoidquality of blind recess portion formation
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the stopper layer locally thicker at the bottom of the blind recess portion compared to the wiring layers. This localized thickness increase ensures high-quality recess formation and proper encapsulant stopping without increasing the overall package thickness, maintaining both dimensional constraints and manufacturing precision

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11049782B2Fan-out semiconductor package
Publication Date: 2021.06.29 SAMSUNG ELECTRONICS CO LTD
  • US11049782B2 patent drawing
  • US11049782B2 patent drawing
  • US11049782B2 patent drawing

AI summary

A fan-out semiconductor package includes a frame including a plurality of wiring layers electrically connected to each other and having a recess portion having a bottom surface on which a stopper layer is disposed, a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer, an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion, and a connection structure disposed on the frame and the active surface and including a redistribution layer electrically connected to the plurality of wiring layers and the connection pad. A thickness of the stopper layer is greater than a thickness of each of the plurality of wiring layers.