Fan-out semiconductor package with recessed frame for multi-chip integration
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Solution Overview
Problem
Fan-out semiconductor packages face structural instability due to thickness differences between semiconductor chips, which can lead to warpage and compromised stability, especially when multiple chips with varying thicknesses are integrated.
Innovation Solution
The design incorporates a frame with recess portions of different depths to accommodate chips of varying thicknesses, along with a connection member and encapsulant to redistribute connection pads and improve structural stability, allowing for the integration of multiple chips with different heights while minimizing step portions and enhancing rigidity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips with different thicknesses are integrated in the package, then the functionality and integration capability are improved, but structural stability deteriorates due to step portions and warpage
Solution Approach 1:
The patent applies local quality by creating recess portions of different depths in the frame to accommodate chips of varying thicknesses. Each recess portion is locally adapted to the specific thickness of the chip it holds, allowing the frame to maintain a uniform top surface while accommodating diverse chip dimensions. This local adaptation enables multi-chip integration without compromising structural stability.
Solution Approach 2:
The patent resolves the thickness difference issue by transitioning from a two-dimensional planar arrangement to a three-dimensional structured arrangement with recess portions at different depths. This dimensional change allows chips of different thicknesses to be accommodated vertically while maintaining a uniform package top surface, eliminating step portions and improving structural stability.
2Adaptability or versatility
If chips of different thicknesses are mounted on a flat substrate, then integration flexibility is improved, but warpage increases due to height differences
Solution Approach 1:
The frame is designed with local quality variations through recess portions of different depths, allowing each chip to be accommodated at its appropriate level. This local adaptation prevents height differences from causing warpage while maintaining integration flexibility for chips of various thicknesses.
Solution Approach 2:
The recess portions are pre-formed in the frame before chip mounting, providing a cushioning effect that absorbs the thickness variations of different chips. This beforehand preparation prevents warpage by ensuring that chips of different thicknesses sit at appropriate levels, eliminating the need for post-mounting adjustments.
3Volume of moving object
If a compact package design is implemented, then space efficiency is improved, but structural rigidity deteriorates when accommodating multiple chips
Solution Approach 1:
The patent utilizes the vertical dimension by creating recess portions at different depths within the compact package volume. This allows multiple chips to be integrated in a space-efficient manner while the frame structure maintains rigidity through its multi-layer construction and recess design that distributes mechanical loads effectively.
Solution Approach 2:
The frame is constructed as a composite structure with multiple insulating layers, wiring layers, and connection via layers, providing both compact dimensions and structural rigidity. The composite nature of the frame allows it to maintain strength while accommodating the complex multi-chip arrangement in a compact package.
Data Source
AI summary
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a first recess portion and a first stopper layer disposed on a bottom surface of the first recess portion; a semiconductor chip disposed in the first recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the first stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the first recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other.