Fan-Out Package Structure With Embedded Die And Redistribution Layers
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization, higher speed, and lower power consumption due to increased leakage current from smaller feature sizes, necessitating innovative packaging techniques for semiconductor devices.
Innovation Solution
A fan-out package structure is developed, where a semiconductor die is embedded in a molding compound layer with redistribution layers and interconnect structures formed over it, enabling efficient electrical connections through solder balls and under-bump metallization structures, reducing conduction losses and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but leakage current increases
Solution Approach 1:
The patent transitions from planar 2D integration to 3D vertical integration by stacking multiple semiconductor dies and interconnect layers. This dimensional change allows continued increase in integration density without further reducing feature size, thereby avoiding the leakage current problem associated with miniaturization while still achieving higher component density through vertical stacking of die stacks.
2Area of stationary object
If conventional packaging is used, then manufacturing is simpler, but additional surface area for interconnects cannot be provided
Solution Approach 1:
The patent segments the package structure into multiple discrete die stacks, each containing a semiconductor die embedded in a molding compound layer with associated interconnect structures. This segmentation allows each stack to be independently formed and then assembled into the final package, providing the necessary surface area for interconnects while managing complexity through modular construction rather than a monolithic complex structure.
Solution Approach 2:
The patent embeds the semiconductor die within the molding compound layer, creating a nested configuration where the die is surrounded by the molding material. This nesting provides additional surface area on the top surface of the molding compound for forming interconnect structures without increasing the overall footprint, effectively hiding the complexity within the nested structure.
3Area of stationary object
If fan-out package structure is implemented, then surface area for interconnects increases, but manufacturing process becomes more complex
Solution Approach 1:
The patent forms the interconnect structures within the molding compound layer during the molding process itself, before final assembly. The redistribution layers are deposited and patterned on the top surface of the molding compound while it is still in the mold, allowing preliminary formation of complex interconnect structures without requiring additional post-assembly manufacturing steps, thereby easing the overall manufacturing process despite the increased surface area.
Data Source
AI summary
A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.