Fan-out Semiconductor Package Pre-formed Redistribution Layers
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Solution Overview
Problem
The existing fan-out semiconductor package manufacturing process faces challenges in reducing semiconductor chip yield due to defects occurring after the redistribution layer is formed, and it struggles with warpage and limited design freedom due to the semiconductor chip being encapsulated before the redistribution layer is formed.
Innovation Solution
The proposed fan-out semiconductor package includes a first connection member with redistribution layers formed before the semiconductor chip is disposed, which reduces the number of layers in the second connection member, improves rigidity, and enhances warpage control, allowing for a wider routing region and better adhesion of the chip, thus addressing yield and design freedom issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the semiconductor chip is encapsulated before the redistribution layer is formed, then the manufacturing process is simplified, but the semiconductor chip yield is reduced due to defects occurring after chip placement
Solution Approach 1:
The redistribution layers are formed in advance on the first connection member before the semiconductor chip is placed. This preliminary formation of redistribution layers allows defect detection and correction before chip attachment, thereby improving chip yield while maintaining manufacturing simplicity through the pre-configured fan-out structure
2Ease of manufacture
If the semiconductor chip is encapsulated before the redistribution layer is formed, then the manufacturing process is simplified, but design freedom is limited
Solution Approach 1:
The first connection member is pre-configured with multiple redistribution layers and routing regions before chip placement. This preliminary structure provides flexible routing options and design freedom for various chip configurations while maintaining a simplified overall manufacturing process through the fan-out package architecture
Solution Approach 2:
The patent utilizes multiple layers (first redistribution layer, second redistribution layer, third redistribution layer) in the vertical dimension to provide routing freedom. By distributing connection terminals across multiple layers and extending them outwardly from the chip region, the design achieves enhanced adaptability without complicating the manufacturing process
3Volume of moving object
If the semiconductor chip is encapsulated before the redistribution layer is formed, then the package structure is compact, but warpage control becomes difficult
Solution Approach 1:
The first connection member with redistribution layers is prepared in advance before chip attachment. This preliminary structure allows for pre-compression application that can control warpage during subsequent packaging steps, maintaining compact package size while improving warpage control through the staged manufacturing approach
Solution Approach 2:
The patent applies compression to the first connection member during the manufacturing process to control warpage. By changing the physical state and mechanical properties of the connection member through compression, the package maintains compact dimensions while achieving better warpage control in the final structure
Data Source
AI summary
The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.