Fan-Out Semiconductor Package With Ring Substrate Heat Dissipation
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Solution Overview
Problem
Die included in a fan out wafer level package (FOWLP) generates a significant amount of heat, necessitating improved heat dissipation.
Innovation Solution
A semiconductor package design incorporating a first redistribution layer (RDL) with a substrate having a rectangular ring shape, a semiconductor chip, heat dissipation blocks, and a molding member, along with a second RDL, featuring redistribution wiring structures to enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a conventional FOWLP structure is used, then the package is compact and manufacturable, but heat dissipation is insufficient
Solution Approach 1:
The substrate is segmented into a rectangular ring shape with multiple openings, creating distinct regions for heat dissipation blocks. This segmentation allows heat to be dissipated through multiple separate paths simultaneously, improving overall heat dissipation performance while maintaining a compact form factor.
Solution Approach 2:
Heat dissipation blocks are positioned in multiple horizontal directions (first, second, third, and fourth directions) around the semiconductor chip, utilizing two-dimensional spatial arrangement. This multi-directional布局 enables heat to be conducted away from the chip through various pathways, significantly enhancing heat dissipation capability.
2Temperature
If heat dissipation blocks are added to improve thermal management, then heat dissipation improves, but device complexity increases
Solution Approach 1:
The substrate serves multiple functions: it provides mechanical support, electrical connection through wiring structures, and thermal management through its rectangular ring shape and openings. The heat dissipation blocks simultaneously conduct heat and are integrated into the substrate structure, reducing the need for separate heat sink components.
Solution Approach 2:
The heat dissipation blocks are merged with the substrate structure, forming an integrated thermal management system. The substrate and heat dissipation blocks work together as a unified structure, eliminating the need for separate heat sink components and reducing overall device complexity.
3Temperature
If multiple heat dissipation paths are created, then heat dissipation efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The rectangular ring-shaped substrate with openings is prepared in advance, creating pre-defined pathways for heat dissipation blocks. This preliminary structuring allows heat dissipation components to be easily positioned and integrated during assembly, simplifying the manufacturing process while ensuring efficient heat dissipation paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design efficiently dissipates heat generated from the semiconductor chip through multiple paths, improving heat dissipation characteristics.
Implementation Method 1
a heat dissipation block between the semiconductor chip and the substrate on the first RDL
Data Source
AI summary
According to some example embodiments, a semiconductor package includes a first redistribution layer (RDL) including a first redistribution wiring structure, a substrate on the first RDL and including a wiring structure and having a rectangular ring shape, a semiconductor chip on the first RDL and in a space defined by the substrate, a heat dissipation block between the semiconductor chip and the substrate on the first RDL, a molding member on the first RDL and covering sidewalls of the semiconductor chip and the heat dissipation block and an inner sidewall of the substrate, and a second RDL on the semiconductor chip, the heat dissipation block, the substrate and the molding member and including a second redistribution wiring structure. A planar area of the heat dissipation block is greater than a planar of the semiconductor chip.