Fan-Out Package-on-Package Substrate Design for Reduced Height
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Solution Overview
Problem
Conventional 3D packaging technologies, such as package-on-package (PoP), face challenges with increased cost, reduced control over vertical interconnection pitch, and higher manufacturing costs due to the need for laser drilling through entire package thickness, which also results in thicker substrates that cause warpage and thermal performance issues.
Innovation Solution
A fan-out package-on-package (Fo-PoP) method involving a substrate with an insulating and conductive layer, where a semiconductor die is disposed in an opening, encapsulated, and further openings are formed to expose the conductive layer, allowing for reduced package height and fine-pitch vertical interconnections without the need for extensive laser drilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling is used to form vertical interconnections through the entire package thickness, then interconnect structures can be formed, but the package height increases and manufacturing cost increases
Solution Approach 1:
The substrate is divided into multiple layers (first substrate layer, second substrate layer) with the semiconductor die embedded between them. Vertical interconnections are formed separately in each layer rather than drilling through the entire package thickness, which reduces the required drill bit length and manufacturing complexity while achieving the same interconnect function
Solution Approach 2:
The semiconductor die is embedded in the substrate and partially encapsulated before forming the vertical interconnections. This preliminary arrangement allows interconnections to be formed only through the necessary substrate thickness rather than the entire package, reducing height and manufacturing difficulty
2Ease of operation
If conventional substrate thickness (100 μm or more) is used, then handling during pick and place operation is easier, but warpage occurs and thermal performance decreases
Solution Approach 1:
The substrate is constructed as a composite structure with multiple layers including a first substrate layer, a semiconductor die, a second substrate layer, and encapsulant material. This composite construction allows optimization of each layer's thickness and material properties to reduce warpage and improve thermal performance while maintaining adequate mechanical strength for handling
Solution Approach 2:
Different regions of the package have different thickness characteristics - the substrate layers are thin in the active area where the die is mounted to improve thermal performance, while the overall package structure maintains sufficient rigidity through the multi-layer composite construction and encapsulant material
3Temperature
If substrate thickness is reduced to 130 μm or less, then thermal performance improves and warpage is reduced, but the substrate becomes susceptible to damage during handling
Solution Approach 1:
The substrate system uses a composite structure with multiple thin layers (first substrate layer, semiconductor die, second substrate layer, encapsulant) that individually have reduced thickness for thermal performance, but collectively provide the mechanical strength and damage resistance needed for reliable handling through their combined structural integrity
Data Source
AI summary
A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die.