Fan-Out Semiconductor Package Layout for Reliable High Terminal Density
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Solution Overview
Problem
The increasing complexity and miniaturization of electronic devices require semiconductor packages with enhanced connection reliability and productivity, particularly in fan-out designs where interference between connection terminals is a concern.
Innovation Solution
A semiconductor package design featuring a dual wiring structure with redistribution patterns and insulating layers, encapsulant, and conductive connection layers to secure and connect top and bottom connection pads, ensuring reliable electrical connections and increased productivity through efficient manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of connection terminals is increased for highly integrated semiconductor chips, then the capacity and functionality are improved, but interference between connection terminals occurs and connection reliability deteriorates
Solution Approach 1:
The patent implements a fan-out wiring structure where connection terminals are redistributed from a compact two-dimensional arrangement to an expanded layout that utilizes both horizontal and vertical dimensions. The signal paths are routed through multiple layers and redirected away from each other, transforming the terminal arrangement from a planar configuration to a three-dimensional distributed structure that reduces interference while maintaining high terminal count
Solution Approach 2:
The patent divides the wiring structure into multiple segments including first and second wiring structures with separate redistribution patterns. Connection terminals are grouped into different segments that are spatially separated and independently routed, preventing interference between adjacent terminals while maintaining electrical connectivity through distributed connection paths
2Reliability
If the distance between connection terminals is increased to prevent interference, then connection reliability is improved, but the area occupied by the package increases
Solution Approach 1:
The patent employs a nested multi-layer wiring structure where first and second wiring structures are stacked vertically with redistribution patterns at different levels. Connection terminals are arranged in nested configurations where inner terminals connect through vertical vias and outer terminals are redistributed around the perimeter, achieving both increased terminal spacing and compact overall package footprint through vertical integration
Solution Approach 2:
The patent transitions from a two-dimensional terminal layout to a three-dimensional fan-out structure that utilizes vertical stacking of wiring layers. By redistributing terminals across multiple height levels and routing paths, the design achieves increased effective spacing between terminals without proportionally increasing the horizontal package area, as the expansion occurs primarily in the vertical dimension
3Object-affected harmful factors
If a fan-out semiconductor package is designed to increase distance between terminals, then interference is reduced, but device complexity increases
Solution Approach 1:
The patent divides the complex wiring into manageable segments including first redistribution patterns, second redistribution patterns, and intermediate connection structures. Each segment performs a specific function (input terminal redistribution, output terminal redistribution, inter-layer connection) and can be independently designed and manufactured, reducing overall system complexity despite the fan-out configuration
Solution Approach 2:
The patent employs universal wiring structure components such as standardized redistribution insulating layers, conductive connection layers, and encapsulant materials that serve multiple functions simultaneously. These components provide electrical insulation, mechanical support, stress relief, and interference shielding all at once, reducing the need for additional specialized structures and simplifying the overall design
Data Source
AI summary
A semiconductor package includes a first wiring structure including a plurality of first redistribution patterns having a plurality of first bottom connection pads and a plurality of first top connection pads and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns, a second wiring structure including a plurality of second redistribution patterns having a plurality of second bottom connection pads and a plurality of second top connection pads and a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a semiconductor chip interposed between the first wiring structure and the second wiring structure, an encapsulant filling a space between the first wiring structure and the second wiring structure, and a plurality of connection structures passing through the encapsulant and connecting the plurality of first top connection pads to the plurality of second bottom connection pads and arranged around the semiconductor chip.