Fan-Out Package Extension Structure for I/O Terminal Spacing
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Solution Overview
Problem
Existing semiconductor packages face challenges in ensuring reliable connection terminals for highly integrated semiconductor chips with increased I/O connections, particularly in preventing interference between terminals.
Innovation Solution
A semiconductor package design featuring a fan-out panel level package (FOPLP) with an extension structure that includes an extension base layer and via structures, providing a mounting space for a semiconductor chip and ensuring electrical connectivity through a filling insulating layer and additional wiring structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fan-out semiconductor packages are used to increase distances between connection terminals, then interference between terminals is prevented, but device complexity increases
Solution Approach 1:
The package structure is divided into multiple functional layers including a substrate, build-up layers with redistribution patterns, and via structures. This segmentation allows connection terminals to be spatially separated across different layers, increasing distance between terminals while maintaining organized electrical connections through the layered architecture.
Solution Approach 2:
The patent utilizes vertical stacking of multiple build-up layers and redistribution patterns in the Z-direction to achieve terminal separation. By distributing connection terminals across multiple vertical layers rather than only in-plane, the design increases effective distance between terminals while managing complexity through three-dimensional organization.
2Adaptability or versatility
If the number of I/O connection terminals is increased for highly integrated semiconductor chips, then chip functionality is enhanced, but terminal interference increases
Solution Approach 1:
The high-density I/O terminals are segmented and distributed across multiple build-up layers and redistribution pattern sets. This segmentation allows the increased number of terminals to be spatially organized with adequate spacing, maintaining both high functionality and reliable connections by preventing terminal interference through multi-layer distribution.
Solution Approach 2:
The redistribution patterns and via structures serve multiple functions: they provide electrical connections, enable terminal spacing, and facilitate signal routing. This multi-functionality allows the package to support increased I/O terminals for enhanced chip functionality while maintaining connection reliability through the same structural elements.
3Reliability
If extension structures with multiple via structures are implemented, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The extension structures and via holes are formed preliminarily during the build-up process before final chip mounting. By pre-forming the via structures and redistribution patterns in the substrate and build-up layers, the patent ensures electrical connectivity is established in advance, simplifying subsequent assembly steps while maintaining manufacturing feasibility through standardized multi-layer PCB processes.
Data Source
AI summary
A semiconductor package includes a first wiring structure, an extension structure disposed on the first wiring structure, including an extension base layer and a plurality of via structures, and having a mounting space passing through the extension base layer. The plurality of via structures include a plurality of via connection patterns, a semiconductor chip disposed in the mounting space and electrically connected to the first wiring structure, a filling insulating layer filling the mounting space, and a second wiring structure disposed on the extension structure and the filling insulating layer and electrically connected to the first wiring structure. Lowermost via connection patterns, among the plurality of via connection patterns, include a plurality of first lower connection pads, and the extension base layer includes base dams respectively passing through the plurality of first lower connection pads.