Fan-out Semiconductor Package with Interconnection Member
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Solution Overview
Problem
Current fan-in semiconductor packages face challenges in miniaturization and direct mounting on electronic device main boards due to spatial limitations and the need for interposer substrates, which restrict their application for compact semiconductor chips with numerous I/O terminals.
Innovation Solution
The fan-out semiconductor package design includes a redistribution layer, an interconnection member with a through hole, a semiconductor chip exposed within the hole, and a protective layer between the redistribution layer and the interconnection member, allowing for a compact size and standardized ball layout, enabling direct mounting on electronic device main boards without separate interposer substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fan-in semiconductor package structure is used, then I/O terminals can be connected, but spatial limitations prevent miniaturization and direct mounting on main boards
Solution Approach 1:
The patent transitions from fan-in configuration where I/O terminals are arranged within the chip footprint to fan-out configuration where terminals are redistributed to a larger area beyond the chip boundaries. This dimensional expansion allows the package to be mounted directly on main boards without requiring separate interposer substrates, effectively resolving the spatial limitation while enabling direct mounting capability
Solution Approach 2:
The patent segments the I/O terminal arrangement by separating the chip body from the terminal distribution area through an interconnection member with through holes. The semiconductor chip is disposed within the interconnection member, and terminals are redistributed through the structure, allowing independent optimization of chip size and terminal layout, thus achieving miniaturization while maintaining mounting capability
2Adaptability or versatility
If interposer substrates are used for mounting, then connection is enabled, but package complexity and size increase
Solution Approach 1:
The patent merges the functions of the interposer substrate and the semiconductor package into a single integrated structure. The interconnection member with through holes serves both as a mounting substrate and as part of the package structure, eliminating the need for separate interposer substrates. This consolidation maintains mounting adaptability while significantly reducing package complexity and overall size
3Volume of moving object
If chip size is reduced for miniaturization, then compactness is achieved, but thermal and electrical management becomes more difficult
Solution Approach 1:
The patent introduces an interconnection member as an intermediary structure between the semiconductor chip and the external environment. This interconnection member with through holes provides dedicated pathways for thermal and electrical management, allowing the miniaturized chip to maintain excellent thermal and electrical characteristics by mediating heat dissipation and electrical connections through the redistributed terminal structure
Data Source
AI summary
A fan-out semiconductor package includes a redistribution layer, an interconnection member, a semiconductor chip, and a protective layer. The interconnection member has a through hole disposed on the redistribution layer. The semiconductor chip is disposed on the redistribution layer exposed within the through hole. The protective layer is formed between the redistribution layer and the interconnection member, and coupled to the interconnection member to protect the interconnection member.