Fan-Out Semiconductor Package Via Redistribution
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Solution Overview
Problem
Current fan-in semiconductor packages face challenges in miniaturization and reliability due to spatial limitations and signal loss caused by wire bonding, especially when stacking multiple memory chips, which increases thickness and costs, and requires separate interposer substrates that can lead to warpage and reduced productivity.
Innovation Solution
A fan-out semiconductor package design that stacks multiple semiconductor chips with redistribution layers and vias to connect pads on central portions of active surfaces, eliminating the need for interposer substrates and wire bonding, allowing for efficient redistribution and reduced thickness, and using encapsulants to secure chips without additional tapes, thereby improving signal integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are stacked with wire bonding, then electrical connection is achieved, but signal loss and reduced reliability occur
Solution Approach 1:
The patent extracts and eliminates the wire bonding process from the chip stacking configuration. Instead of using separate wire bonds to connect chips, the invention integrates direct pad-to-pad electrical connections through the stacked chip structure, removing the intermediate wire bonding step that causes signal loss and reliability issues.
Solution Approach 2:
The patent merges the electrical connection function directly into the chip stacking structure itself. By aligning and contacting pads on adjacent chip surfaces, the invention combines the mechanical stacking and electrical connection functions into a single integrated structure, eliminating the need for separate wire bonding processes.
2Adaptability or versatility
If interposer substrates are used to connect chips, then redistribution of connection terminals is achieved, but device thickness increases
Solution Approach 1:
The patent extracts and removes the interposer substrate from the chip stacking structure. By eliminating this intermediate substrate layer, the invention achieves terminal redistribution directly through the stacked chips themselves, significantly reducing the overall package thickness while maintaining the ability to redistribute connection terminals.
Solution Approach 2:
The patent transitions from a planar redistribution approach (using interposer substrates) to a vertical/three-dimensional redistribution approach. By stacking chips vertically and redistributing terminals through the Z-axis layers, the invention achieves terminal adaptation without increasing package thickness in the X-Y plane.
3Stability of the object's composition
If multiple chips are stacked with additional securing tapes, then chip positioning is achieved, but device complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the additional securing tapes from the chip stacking structure. By designing the chip pads and stacking geometry to provide inherent mechanical stability and positioning, the invention achieves secure chip positioning without requiring extra tape layers, thereby reducing structural complexity and manufacturing cost.
4Reliability
If chips are connected through overlapping vias, then electrical connection is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the electrical connection path into distinct, non-overlapping via structures. Instead of requiring precise overlapping of vias through multiple chip layers, the invention uses sequentially arranged vias that connect pads through each individual chip layer, reducing the cumulative alignment precision requirements across multiple layers.
Data Source
AI summary
The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.