Fan-Out Package Structure for Warpage-Controlled Bump Reliability
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Solution Overview
Problem
Integrated fan-out technology in semiconductor packaging faces challenges such as warpage issues, which affect the reliability and yield of bump joints in redistribution circuit layers.
Innovation Solution
A method involving the use of a carrier with a de-bonding layer, over-molding, and selective grinding to minimize warpage, followed by the formation of front and back-side redistribution circuit layers to enhance electrical connections and minimize defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated fan-out packaging technique is used to achieve compactness and high performance, then integration density and electrical performance are improved, but warpage issues occur affecting reliability
Solution Approach 1:
The patent divides the packaging structure into multiple layers including carrier, mold compound, and redistribution circuit layers, with each layer serving specific functions to manage stress and prevent warpage while maintaining high integration density
Solution Approach 2:
The patent modifies physical parameters such as material selection for the carrier and mold compound, layer thickness ratios, and processing temperatures to control thermal expansion differences and minimize warpage during the packaging process
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into given area, but manufacturing precision and defect risk increase
Solution Approach 1:
The patent transitions from planar 2D integration to 3D vertical stacking with multiple redistribution circuit layers, allowing higher integration density while maintaining larger lateral feature sizes that are easier to manufacture with controlled precision
Solution Approach 2:
The patent implements nested interconnect structures where multiple conductive layers and vias are stacked vertically, enabling high integration density through three-dimensional space utilization rather than lateral miniaturization
3Reliability
If warpage is minimized through process control to improve bump joint yield, then manufacturing complexity and process steps increase
Solution Approach 1:
The patent performs preliminary warpage compensation by carefully selecting and pre-characterizing materials with specific thermal expansion coefficients before assembly, and by designing the layer stack-up configuration to inherently balance stresses, preventing warpage before it occurs rather than correcting it later
Data Source
AI summary
A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.