Fan-out semiconductor package warpage control
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Solution Overview
Problem
Conventional fingerprint sensor packages with BGA substrates have long sensing distances, reduced sensitivity, and significant warpage issues due to thick substrates and bonding wires, making them unsuitable for thin and compact designs like under-display applications.
Innovation Solution
A fan-out semiconductor package with a core member having through-vias and a semiconductor chip with a fingerprint recognition function, where the connection pads are redistributed using an insulating layer and vias to reduce thickness and sensing distance, and a passivation layer is strategically placed to control warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a BGA substrate with bonding wires is used for fingerprint sensor packaging, then the sensor can be mounted and connected, but the sensing distance becomes long and sensitivity is reduced
Solution Approach 1:
The patent transitions from a conventional vertical mounting approach to a fan-out planar configuration where connection pads are redistributed horizontally on the same substrate plane. This dimensional redistribution eliminates the need for vertical bonding wires and reduces the sensing distance between the fingerprint sensor and the display surface, thereby improving sensitivity while maintaining reliable electrical connections through the redistributed pad layout.
2Strength
If a thick BGA substrate is used for packaging, then structural support is provided, but warpage occurs and thickness is increased
Solution Approach 1:
The patent segments the monolithic thick BGA substrate into a thin substrate with separate redistribution layers. The connection pads are divided and redistributed across multiple layers and locations on the thin substrate, providing the necessary structural support through the layered construction while eliminating the warpage issues associated with thick single-layer substrates. This segmentation allows for better stress distribution and flatness control.
3Reliability
If bonding wires are used for electrical connection, then the sensor can be connected to the substrate, but the sensing distance increases and sensitivity decreases
Solution Approach 1:
The patent extracts and eliminates the bonding wire interconnection structure from the packaging design. Instead of using bonding wires to connect the fingerprint sensor to the BGA substrate, the connection pads are directly redistributed on the substrate surface, removing the intermediate bonding wire layer. This extraction reduces the sensing distance and eliminates the sensitivity degradation caused by the bonding wire structure, while maintaining reliable electrical connections through the direct pad redistribution approach.
4Length of stationary object
If the package thickness is reduced for under-display application, then integration is improved, but warpage control becomes difficult
Solution Approach 1:
The patent employs asymmetric redistribution of connection pads across different locations and layers of the thin substrate. By strategically placing pads with different functions (signal, power, ground) at asymmetric positions and depths, the design achieves both thickness reduction and warpage control. The asymmetric multi-layer redistribution structure provides mechanical stability and flatness while maintaining the reduced overall package thickness required for under-display integration.
Data Source
AI summary
A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.