Fan-Out Wafer Level Packaging Structure with Integrated Sealing Layer

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Solution Overview

Problem

The existing fan out wafer level packaging methods face challenges in achieving a smaller package size, improved stability, and reliability due to issues with multilayer material sealing layers, alignment deviations, and increased thickness, which affect the yield and complexity of the packaging process.

Innovation Solution

A chip packaging method involving a first chip with a smaller area and a second chip with a larger area, where the second chip's contact pads are exposed to form a material sealing layer that clads both chips directly, reducing thickness requirements and stabilizing the bonding between the chips, thereby simplifying the electrical interconnection process and minimizing the risk of open circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fan out wafer level packaging method is used with multilayer material sealing layers, then electrical interconnections can be formed, but the package size increases and manufacturing complexity increases due to alignment deviations and cracking/peeling issues

Engineering Contradiction:

Improvepackaging structure stabilityVSAvoidpackaging process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the first chip and second chip into a single integrated packaging structure where the material sealing layer is formed as one continuous layer over both chips simultaneously. This eliminates the need for separate multilayer sealing processes, reducing alignment deviations and manufacturing complexity while improving structural stability and reliability.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If multilayer material sealing layers are used to seal both chips, then electrical interconnections are achieved, but the packaging structure thickness increases and cracking/peeling occurs

Engineering Contradiction:

Improvesealing layer stabilityVSAvoidpackaging structure thickness

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent forms a single integrated material sealing layer that simultaneously seals both the first chip and second chip, eliminating the need for multiple sequential sealing layers. This reduces the overall packaging structure thickness while preventing cracking and peeling issues associated with multilayer constructions, thereby improving sealing layer stability and reliability.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If conventional packaging method is used, then chips can be packaged, but the package size is large due to increased thickness and multilayer structures

Engineering Contradiction:

Improvebonding stabilityVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSVolume of moving object

Solution Approach 1:

The patent integrates both chips into a single packaging structure with a unified material sealing layer, eliminating the need for separate multilayer sealing structures. This merging approach reduces the overall package size and thickness while maintaining bonding stability through the continuous sealing layer that simultaneously secures both chips.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for a more stable and reliable packaging structure with reduced size, improved yield, and simplified process steps, addressing the challenges of cracking and peeling in multilayer sealing layers and alignment deviations.

Implementation Method 1

forming a material sealing layer on the surface of the substrate holder, where the material sealing layer clads the first chip and the second chip

Methodology Applied

Scientific EffectAdhesion: Adhesive

Implementation Method 2

forming first electrical interconnections and second electrical interconnections in the material sealing layer, where the first electrical interconnections are electrically connected to the first contact pads, and the second electrical interconnections are electrically connected to the second contact pads

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10276540B2Chip packaging method and chip packaging structure

Publication Date: 2019.04.30 CHINA WAFER LEVEL CSP

AI summary

A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a fist surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.